Cross Reference: /vbox/src/VBox/VMM/VMMR3/EMRaw.cpp

Lines Matching defs:Cpu
459     DISCPUSTATE Cpu;
460     int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
465         if (!(Cpu.fPrefix & (DISPREFIX_REP | DISPREFIX_REPNE)))
467             switch (Cpu.pCurInstr->uOpcode)
472                     rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
479                     rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
484         else if (Cpu.fPrefix & DISPREFIX_REP)
486             switch (Cpu.pCurInstr->uOpcode)
492                     rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
500                     rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
512             pCtx->rip += Cpu.cbInstr;
709     DISCPUSTATE Cpu;
715     rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
718         if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
733         switch (Cpu.pCurInstr->uOpcode)
812         DISCPUSTATE Cpu;
813         rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
815             &&  Cpu.pCurInstr->uOpcode == OP_IRET)
996     DISCPUSTATE Cpu;
999     rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1004         switch (Cpu.pCurInstr->uOpcode)
1029                 if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
1032                     Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
1033                     Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
1034                     STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
1039                     Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1040                     Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1041                     STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1074                 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1083             switch (Cpu.pCurInstr->uOpcode)
1087                     Assert(Cpu.cbInstr == 1);
1088                     pCtx->rip += Cpu.cbInstr;
1094                     EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1095                     Assert(Cpu.cbInstr == 1);
1096                     pCtx->rip += Cpu.cbInstr;
1133                     rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1138                         if (    Cpu.pCurInstr->uOpcode == OP_MOV_CR
1139                             &&  Cpu.Param1.fUse == DISUSE_REG_CR /* write */