Lines Matching defs:uEax
552 pLegacy->uEax = pLeaf->uEax;
648 * @param uEax The EAX value.
656 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
669 pNew->uEax = uEax;
1117 uint32_t uEax, uEbx, uEcx, uEdx;
1118 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1123 if ( uEax > uLeaf
1124 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1127 uint32_t cLeaves = uEax - uLeaf + 1;
1130 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1141 && ( uEax
1173 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1183 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1185 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1193 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1209 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1212 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1213 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1214 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1215 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1232 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1295 pDefUnknown->uEax = 0;
1358 pDefUnknown->uEax = auLast[0];
1536 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1540 pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1541 pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1542 pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1550 pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1867 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1915 pLeaf->uEax = u32;
1977 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2019 pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2068 pLegacyLeaf->uEax = pLeaf->uEax;
2159 NewLeaf.uEax = UINT32_C(0x40000001);
2168 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2193 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2194 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2195 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2200 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2208 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2209 pStdFeatureLeaf->uEax = uNew;
2235 uint32_t uLimit = pCurLeaf->uEax;
2240 pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2247 pCurLeaf->uEax = uLimit = 3;
2250 pCurLeaf->uEax = uLimit;
2267 uint32_t uLimit = pCurLeaf->uEax;
2273 pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2277 pCurLeaf->uEax = uLimit;
2295 uint32_t uLimit = pCurLeaf->uEax;
2301 pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2305 pCurLeaf->uEax = uLimit;
2330 pCurLeaf->uEax = 0;
2462 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2704 if ((pCurLeaf->uEax & 0xff) > 1)
2706 LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2707 pCurLeaf->uEax &= UINT32_C(0xffffff01);
2727 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2744 pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2752 pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2772 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2824 pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2894 pCurLeaf->uEax = 0;
2945 pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2951 pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2953 while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2954 pCurLeaf->uEax++;
2961 pCurLeaf->uEax = 0;
2971 pCurLeaf->uEax = 0;
3029 pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3033 pCurLeaf->uEax &= 0;
3050 pCurLeaf->uEax = 0;
3157 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3207 pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3249 pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3278 uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3281 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3282 pCurLeaf->uEax |= ((cCores - 1) & 0xfff) << 14;
3284 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3296 pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3970 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3976 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4001 NewLeaf.uEax = CpuId.uEax;
4108 Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4125 Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4126 Leaf.uEax |= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4127 Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4128 Leaf.uEax |= UINT32_C(2) << 5;
4167 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4177 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4184 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4189 &aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4393 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4394 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4395 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4400 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4401 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4402 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4488 CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4489 || aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4491 if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4492 && aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4494 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4504 CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4505 || !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4507 if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4515 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4518 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4519 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4520 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4521 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4522 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4786 && ( pCurLeaf->uEax
4791 uint64_t fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4799 if (pCurLeaf && pCurLeaf->uEax)
4801 N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4820 if (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx)
4824 &RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4826 || RawHost.uEax != pCurLeaf->uEax)
4829 uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5293 uint32_t uEAX = pCurLeaf->uEax;
5317 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5348 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5373 pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5404 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5415 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5417 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5423 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5424 cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5440 && (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx) )
5443 pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5452 if (Host.uEax || Host.uEbx || Host.uEcx || Host.uEdx)
5455 Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5496 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5500 pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5501 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5546 uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5561 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5569 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5570 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5578 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5583 && ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8))
5584 || (uLeaf == 0x7 && Host.uEax == 0)
5604 "Supports:", paLeaves[0].uEax);
5625 ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5626 cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5628 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5646 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5647 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5649 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5666 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5674 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5675 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5683 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5688 && (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) )
5701 &pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5706 uint32_t uEAX = pCurLeaf->uEax;
5724 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5736 *pu32++ = pCurLeaf->uEax;
5743 *pu32++ = pCurLeaf->uEax;
5751 *pu32++ = pCurLeaf->uEax;
5761 uint32_t uEAX = pCurLeaf->uEax;
5799 uint32_t uEAX = pCurLeaf->uEax;
5847 ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5855 uint32_t uEAX = pCurLeaf->uEax;
5880 ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5881 cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5882 ? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5884 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5896 pCurLeaf->uEax);
5900 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);