Lines Matching defs:pVM
98 static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
99 static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
100 static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
101 static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102 static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103 static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104 static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105 static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106 static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107 static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
544 * @param pVM Pointer to the VM.
546 static void cpumR3CheckLeakyFpu(PVM pVM)
559 for (VMCPUID i = 0; i < pVM->cCpus; i++)
560 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
572 * @param pVM Pointer to the VM.
574 VMMR3DECL(int) CPUMR3Init(PVM pVM)
582 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
607 PVMCPU pVCpu = &pVM->aCpus[i];
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
627 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
630 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
635 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
636 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
637 if (!pVM->cpum.s.HostFeatures.fMmx)
638 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
639 if (!pVM->cpum.s.HostFeatures.fTsc)
640 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
645 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
646 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
652 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
653 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
660 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
661 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
663 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx\n", pVM->cpum.s.fXStateHostMask, fXStateHostMask));
668 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
673 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
677 for (VMCPUID i = 0; i < pVM->cCpus; i++)
679 PVMCPU pVCpu = &pVM->aCpus[i];
682 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
683 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
687 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
688 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
692 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
693 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
706 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
716 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
717 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
718 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
719 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
720 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
721 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
723 rc = cpumR3DbgInit(pVM);
730 cpumR3CheckLeakyFpu(pVM);
735 rc = cpumR3InitCpuIdAndMsrs(pVM);
738 CPUMR3Reset(pVM);
750 * @param pVM The VM.
752 VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
756 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
757 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
759 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
761 PVMCPU pVCpu = &pVM->aCpus[iCpu];
762 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
763 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
764 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
775 * @param pVM Pointer to the VM.
778 VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
790 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
791 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
792 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
803 * @param pVM Pointer to the VM.
805 VMMR3DECL(int) CPUMR3Term(PVM pVM)
808 for (VMCPUID i = 0; i < pVM->cCpus; i++)
810 PVMCPU pVCpu = &pVM->aCpus[i];
818 NOREF(pVM);
829 * @param pVM Pointer to the cross context VM structure.
834 VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
920 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
939 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
944 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
978 * @param pVM Pointer to the VM.
980 VMMR3DECL(void) CPUMR3Reset(PVM pVM)
982 for (VMCPUID i = 0; i < pVM->cCpus; i++)
984 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
987 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
990 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
991 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1004 * @param pVM Pointer to the VM.
1008 static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1011 cpumR3SaveCpuId(pVM, pSSM);
1020 * @param pVM Pointer to the VM.
1023 static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1028 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1030 PVMCPU pVCpu = &pVM->aCpus[i];
1037 SSMR3PutU32(pSSM, pVM->cCpus);
1038 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1039 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1041 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1053 cpumR3SaveCpuId(pVM, pSSM);
1061 static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1064 pVM->cpum.s.fPendingRestore = true;
1072 static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1120 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1122 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1138 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1142 || pVM->cCpus == 1,
1143 ("cCpus=%u\n", pVM->cCpus),
1156 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1158 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1185 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1187 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1188 bool const fValid = HMIsEnabled(pVM)
1225 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1226 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1231 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1233 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1243 pVM->cpum.s.fPendingRestore = false;
1249 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1262 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
1264 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
1267 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
1269 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
1272 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
1274 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
1276 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
1328 AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
1368 static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1374 if (pVM->cpum.s.fPendingRestore)
1380 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1381 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1383 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1403 * @param pVM Pointer to the VM.
1405 VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1407 return pVM->cpum.s.fPendingRestore;
1461 * @param pVM Pointer to the VM.
1468 static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1471 NOREF(pVM);
1681 * @param pVM Pointer to the VM.
1685 static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1687 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1688 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1689 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1690 cpumR3InfoHost(pVM, pHlp, pszArgs);
1738 * @param pVM Pointer to the VM.
1742 static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1749 PVMCPU pVCpu = VMMGetCpu(pVM);
1751 pVCpu = &pVM->aCpus[0];
1756 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1763 * @param pVM Pointer to the VM.
1767 static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1772 PVMCPU pVCpu = VMMGetCpu(pVM);
1774 pVCpu = &pVM->aCpus[0];
1786 * @param pVM Pointer to the VM.
1790 static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1795 PVMCPU pVCpu = &pVM->aCpus[0];
1799 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
1800 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1807 * @param pVM Pointer to the VM.
1811 static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1822 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1906 PVM pVM;
1948 if ( !HMIsEnabled(pState->pVM)
1949 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1951 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
1959 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2009 * @param pVM Pointer to the VM.
2017 VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2026 State.pVM = pVM;
2092 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2106 * @param pVM Pointer to the VM.
2110 VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2115 pVM->cpum.s.CR4.OrMask &= fAnd;
2116 pVM->cpum.s.CR4.OrMask |= fOr;
2179 * @param pVM Pointer to the VM.
2181 VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
2187 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2188 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2190 PVMCPU pVCpu = &pVM->aCpus[i];
2194 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2207 * @param pVM Pointer to the VM.
2209 VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2223 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2225 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */