Lines Matching refs:u32Msr
1274 if (pGuestMsr->u32Msr == uMsr)
1294 pGuestMsr->u32Msr = uMsr;
1300 pHostMsr->u32Msr = uMsr;
1313 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1336 if (pGuestMsr->u32Msr == uMsr)
1348 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1354 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1395 if (pGuestMsr->u32Msr == uMsr)
1418 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1424 if (pHostMsr->u32Msr == MSR_K6_EFER)
1427 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1678 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1679 pGuestMsr->u32Msr, cMsrs));
1681 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1682 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1683 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1690 rc = hmR0VmxGetMsrPermission(pVCpu, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1692 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1699 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1700 pGuestMsr->u32Msr, cMsrs));
1701 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1702 pGuestMsr->u32Msr, cMsrs));
4781 Log4(("Load[%RU32]: MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", pVCpu->idCpu, i, pMsr->u32Msr,
4832 Log4(("Load[%RU32]: MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", pVCpu->idCpu, MSR_K6_EFER,
6327 switch (pMsr->u32Msr)
6339 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr, cMsrs));
6340 pVCpu->hm.s.u32HMError = pMsr->u32Msr;