Lines Matching refs:u32GuestCR4
4025 uint32_t u32GuestCR4 = pMixedCtx->cr4;
4028 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32GuestCR4);
4030 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR4_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR4));
4042 u32GuestCR4 &= ~X86_CR4_VME;
4051 u32GuestCR4 |= X86_CR4_PSE;
4053 u32GuestCR4 &= ~X86_CR4_PAE;
4069 u32GuestCR4 &= ~X86_CR4_PAE;
4076 u32GuestCR4 |= X86_CR4_PAE;
4094 u32GuestCR4 |= uSetCR4;
4095 u32GuestCR4 &= uZapCR4;
4098 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", pVCpu->idCpu, u32GuestCR4, uSetCR4, uZapCR4));
4099 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
9463 uint32_t u32GuestCR4;
9464 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCR4);
9466 HMVMX_CHECK_BREAK((u32GuestCR4 & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);
9467 HMVMX_CHECK_BREAK(!(u32GuestCR4 & ~uZapCR4), VMX_IGS_CR4_FIXED0);
9552 HMVMX_CHECK_BREAK(u32GuestCR4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
9556 && (u32GuestCR4 & X86_CR4_PCIDE))