Cross Reference: /vbox/src/VBox/VMM/VMMR0/HMVMXR0.cpp

Lines Matching defs:u32Limit
4314         Assert(   (pCtx->cs.u32Limit & 0xfff) == 0xfff
4316         Assert(   !(pCtx->cs.u32Limit & 0xfff00000)
4341             Assert(   (pCtx->ss.u32Limit & 0xfff) == 0xfff
4343             Assert(   !(pCtx->ss.u32Limit & 0xfff00000)
4354             Assert(   (pCtx->ds.u32Limit & 0xfff) == 0xfff
4356             Assert(   !(pCtx->ds.u32Limit & 0xfff00000)
4368             Assert(   (pCtx->es.u32Limit & 0xfff) == 0xfff
4370             Assert(   !(pCtx->es.u32Limit & 0xfff00000)
4382             Assert(   (pCtx->fs.u32Limit & 0xfff) == 0xfff
4384             Assert(   !(pCtx->fs.u32Limit & 0xfff00000)
4396             Assert(   (pCtx->gs.u32Limit & 0xfff) == 0xfff
4398             Assert(   !(pCtx->gs.u32Limit & 0xfff00000)
4433         Assert(pCtx->cs.u32Limit == 0xffff);
4437         Assert(pCtx->ss.u32Limit == 0xffff);
4441         Assert(pCtx->ds.u32Limit == 0xffff);
4445         Assert(pCtx->es.u32Limit == 0xffff);
4449         Assert(pCtx->fs.u32Limit == 0xffff);
4453         Assert(pCtx->gs.u32Limit == 0xffff);
4488     rc     = VMXWriteVmcs32(idxLimit,  pSelReg->u32Limit);  /* 32-bit guest segment limit field. */
4600               pMixedCtx->cs.u64Base, pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
4614         uint32_t u32Limit        = 0;
4621             u32Limit        = pMixedCtx->tr.u32Limit;
4641             u32Limit        = HM_VTX_TSS_SIZE;
4655         Assert(   (u32Limit & 0xfff) == 0xfff
4657         Assert(   !(pMixedCtx->tr.u32Limit & 0xfff00000)
4661         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT,         u32Limit);              AssertRCReturn(rc, rc);
4697         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT,         pMixedCtx->ldtr.u32Limit);    AssertRCReturn(rc, rc);
4710             Assert(   (pMixedCtx->ldtr.u32Limit & 0xfff) == 0xfff
4712             Assert(   !(pMixedCtx->ldtr.u32Limit & 0xfff00000)
6485     pSelReg->u32Limit = u32Val;
6526                    idxSel, u32Val, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
9644             HMVMX_CHECK_BREAK(   (pCtx->cs.u32Limit & 0xfff) == 0xfff
9646             HMVMX_CHECK_BREAK(   !(pCtx->cs.u32Limit & 0xfff00000)
9675                 HMVMX_CHECK_BREAK(   (pCtx->ss.u32Limit & 0xfff) == 0xfff
9677                 HMVMX_CHECK_BREAK(   !(pCtx->ss.u32Limit & 0xfff00000)
9691                 HMVMX_CHECK_BREAK(   (pCtx->ds.u32Limit & 0xfff) == 0xfff
9693                 HMVMX_CHECK_BREAK(   !(pCtx->ds.u32Limit & 0xfff00000)
9707                 HMVMX_CHECK_BREAK(   (pCtx->es.u32Limit & 0xfff) == 0xfff
9709                 HMVMX_CHECK_BREAK(   !(pCtx->es.u32Limit & 0xfff00000)
9723                 HMVMX_CHECK_BREAK(   (pCtx->fs.u32Limit & 0xfff) == 0xfff
9725                 HMVMX_CHECK_BREAK(   !(pCtx->fs.u32Limit & 0xfff00000)
9739                 HMVMX_CHECK_BREAK(   (pCtx->gs.u32Limit & 0xfff) == 0xfff
9741                 HMVMX_CHECK_BREAK(   !(pCtx->gs.u32Limit & 0xfff00000)
9783             HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
9787             HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
9791             HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
9795             HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
9799             HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
9803             HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
9849         HMVMX_CHECK_BREAK(   (pCtx->tr.u32Limit & 0xfff) == 0xfff
9851         HMVMX_CHECK_BREAK(   !(pCtx->tr.u32Limit & 0xfff00000)