Lines Matching defs:g_HvmR0
167 } g_HvmR0;
346 g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
352 int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353 g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354 if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
359 g_HvmR0.vmx.fSupported = true;
370 g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371 if (RT_SUCCESS(g_HvmR0.lLastError))
372 g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
374 if (RT_SUCCESS(g_HvmR0.lLastError))
377 g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
382 g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
383 g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384 g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
385 g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
386 g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
387 g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
388 g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
389 g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
390 g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
391 g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
392 g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
393 g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
394 g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
396 g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
398 if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
400 g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
401 if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID))
402 g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
404 if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
405 g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
408 if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
426 *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
434 g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
435 if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
439 ASMSetCR4(g_HvmR0.vmx.u64HostCr4 | X86_CR4_VMXE);
450 g_HvmR0.vmx.fSupported = true;
466 g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
467 Assert(g_HvmR0.vmx.fSupported == false);
473 ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
479 if (g_HvmR0.vmx.fSupported)
483 g_HvmR0.lLastError = rc;
488 g_HvmR0.pfnEnterSession = VMXR0Enter;
489 g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
490 g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
491 g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
492 g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
493 g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
494 g_HvmR0.pfnInitVM = VMXR0InitVM;
495 g_HvmR0.pfnTermVM = VMXR0TermVM;
496 g_HvmR0.pfnSetupVM = VMXR0SetupVM;
502 if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
504 g_HvmR0.vmx.fUsePreemptTimer = true;
505 g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
507 g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
513 SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
517 g_HvmR0.lLastError = VERR_VMX_NO_VMX;
534 if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
545 g_HvmR0.lLastError = rc;
552 g_HvmR0.pfnEnterSession = SVMR0Enter;
553 g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
554 g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
555 g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
556 g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
557 g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
558 g_HvmR0.pfnInitVM = SVMR0InitVM;
559 g_HvmR0.pfnTermVM = SVMR0TermVM;
560 g_HvmR0.pfnSetupVM = SVMR0SetupVM;
564 ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
583 g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
584 g_HvmR0.svm.fSupported = true;
588 g_HvmR0.lLastError = rc;
596 g_HvmR0.lLastError = VERR_SVM_NO_SVM;
612 g_HvmR0.fEnabled = false;
614 g_HvmR0.EnableAllCpusOnce = s_OnceInit;
615 for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
617 g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
618 g_HvmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
622 g_HvmR0.pfnEnterSession = hmR0DummyEnter;
623 g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
624 g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
625 g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
626 g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
627 g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
628 g_HvmR0.pfnInitVM = hmR0DummyInitVM;
629 g_HvmR0.pfnTermVM = hmR0DummyTermVM;
630 g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
633 g_HvmR0.fGlobalInit = true;
638 if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
640 LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
662 &g_HvmR0.cpuid.u32AMDFeatureECX,
663 &g_HvmR0.cpuid.u32AMDFeatureEDX);
665 g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
682 g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
685 g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
688 g_HvmR0.lLastError = VERR_HM_NO_CPUID;
694 if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
717 if ( g_HvmR0.vmx.fSupported
718 && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
723 Assert(g_HvmR0.fGlobalInit);
726 for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
728 g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
729 Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
734 Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
735 if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
747 if (g_HvmR0.fGlobalInit)
763 for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
765 if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
767 RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
768 g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
777 if (g_HvmR0.vmx.fSupported)
779 else if (g_HvmR0.svm.fSupported)
838 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
841 Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
849 if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
850 rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
857 if (g_HvmR0.vmx.fSupported)
858 rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
860 rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
881 AssertReturnVoid(g_HvmR0.fGlobalInit);
904 AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
905 ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
910 g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
913 for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
915 Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
916 Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
917 Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
918 Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
923 if ( g_HvmR0.vmx.fSupported
924 && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
933 g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
944 for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
946 Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
950 rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
953 void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
962 && g_HvmR0.fGlobalInit)
986 if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
989 return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1003 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1005 Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1008 Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1021 rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1044 AssertReturnVoid(g_HvmR0.fGlobalInit);
1115 Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1125 ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1127 if (g_HvmR0.fEnabled)
1135 if (g_HvmR0.fGlobalInit)
1147 if (g_HvmR0.vmx.fSupported)
1158 if (g_HvmR0.fGlobalInit)
1169 ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1194 if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1200 pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1201 pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1203 pVM->hm.s.vmx.fUsePreemptTimer &= g_HvmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1204 pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1205 pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1206 pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1207 pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1208 pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1209 pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1210 pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1211 pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1212 pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1213 pVM->hm.s.lLastError = g_HvmR0.lLastError;
1214 pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1242 return g_HvmR0.pfnInitVM(pVM);
1263 return g_HvmR0.pfnTermVM(pVM);
1281 AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1297 if (!g_HvmR0.fGlobalInit)
1304 rc = g_HvmR0.pfnSetupVM(pVM);
1307 if (!g_HvmR0.fGlobalInit)
1333 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1361 AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1374 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1378 rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1383 rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1413 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1415 if ( !g_HvmR0.fGlobalInit
1444 Assert(g_HvmR0.pfnThreadCtxCallback);
1446 g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1466 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1469 AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1479 int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1555 return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1569 Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1570 return &g_HvmR0.aCpuInfo[idCpu];
1583 Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1584 return &g_HvmR0.aCpuInfo[idCpu];
1651 if (!g_HvmR0.vmx.fSupported)
1673 if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1683 if (!g_HvmR0.fEnabled)
1687 if (!g_HvmR0.fGlobalInit)
1715 Assert(g_HvmR0.vmx.fSupported);
1716 if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1720 Assert(g_HvmR0.fEnabled);
1721 Assert(g_HvmR0.fGlobalInit);
1728 VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);