Lines Matching refs:pVCpu
103 static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
336 * @param pVCpu Pointer to the VMCPU.
339 VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
345 if (CPUMIsGuestFPUStateActive(pVCpu))
386 return CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
396 * @param pVCpu Pointer to the VMCPU.
399 VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
405 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
408 cpumR0SaveHostFPUState(&pVCpu->cpum.s);
411 pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
417 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
433 pVCpu->cpum.s.fUseFlags |= CPUM_USED_MANUAL_XMM_RESTORE;
439 cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
446 Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM));
456 * @param pVCpu Pointer to the VMCPU.
459 VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
463 AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
469 if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
471 HMR0SaveFPUState(pVM, pVCpu, pCtx);
472 cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
489 memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], sizeof(aGuestXmmRegs));
495 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE)
505 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
512 memcpy(&pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
516 pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_SYNC_FPU_STATE | CPUM_USED_MANUAL_XMM_RESTORE);
526 * @param pVCpu Pointer to the VMCPU.
528 static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
534 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
535 cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
537 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
538 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
539 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
540 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
542 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
544 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
547 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
553 if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
570 * @param pVCpu The cross context CPU structure for the calling EMT.
572 * @thread EMT(pVCpu)
574 VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
577 bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
583 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
586 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
588 uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
589 HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
591 pVCpu->cpum.s.Guest.dr[6] = uDr6;
597 cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
599 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
600 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
601 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
602 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
605 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
608 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER
614 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
622 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
623 cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
625 ASMSetDR0(pVCpu->cpum.s.Host.dr0);
626 ASMSetDR1(pVCpu->cpum.s.Host.dr1);
627 ASMSetDR2(pVCpu->cpum.s.Host.dr2);
628 ASMSetDR3(pVCpu->cpum.s.Host.dr3);
632 ASMSetDR6(pVCpu->cpum.s.Host.dr6);
633 ASMSetDR7(pVCpu->cpum.s.Host.dr7);
635 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
650 * @param pVCpu The cross context CPU structure for the calling EMT.
652 * @thread EMT(pVCpu)
654 VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
660 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
663 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
665 uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
666 HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
668 pVCpu->cpum.s.Guest.dr[6] = uDr6;
674 cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
676 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
677 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
678 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
679 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
682 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
693 * @param pVCpu The cross context CPU structure for the calling EMT.
695 * @thread EMT(pVCpu)
697 VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
702 cpumR0SaveHostDebugState(pVCpu);
710 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
711 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
716 cpumR0LoadDRx(&pVCpu->cpum.s.Guest.dr[0]);
718 ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
719 ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
720 ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
721 ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
724 ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
726 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
735 * @param pVCpu The cross context CPU structure for the calling EMT.
737 * @thread EMT(pVCpu)
739 VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
744 cpumR0SaveHostDebugState(pVCpu);
750 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
757 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
758 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
763 cpumR0LoadDRx(&pVCpu->cpum.s.Hyper.dr[0]);
765 ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
766 ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
767 ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
768 ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
773 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
1009 * @param pVCpu Pointer to the cross context CPU structure of the
1013 VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1016 pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1017 pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;