Lines Matching defs:rc
142 int rc = MMHyperAlloc(pVM, sizeof(*pNew), 0, MM_TAG_PGM_HANDLERS, (void **)&pNew);
143 if (RT_FAILURE(rc))
144 return rc;
167 rc = pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs(pVM, pNew, pRam);
168 if (rc == VINF_PGM_SYNC_CR3)
169 rc = VINF_PGM_GCPHYS_ALIASED;
178 if (rc != VINF_SUCCESS)
179 Log(("PGMHandlerPhysicalRegisterEx: returns %Rrc (%RGp-%RGp)\n", rc, GCPhys, GCPhysLast));
180 return rc;
212 int rc = VINF_SUCCESS;
229 if (rc2 != VINF_SUCCESS && rc == VINF_SUCCESS)
230 rc = rc2;
242 Log(("pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs: flushing guest TLBs; rc=%d\n", rc));
245 Log(("pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs: doesn't flush guest TLBs. rc=%Rrc; sync flags=%x VMCPU_FF_PGM_SYNC_CR3=%d\n", rc, VMMGetCpu(pVM)->pgm.s.fSyncFlags, VMCPU_FF_IS_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3)));
247 return rc;
395 int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, ppRamHint);
396 if ( RT_SUCCESS(rc)
402 rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhys, pPage, false /*fFlushPTEs*/, &fFlushTLBs);
403 if (RT_SUCCESS(rc) && fFlushTLBs)
406 AssertRC(rc);
409 AssertRC(rc);
434 int rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPage, true /*fFlushPTEs*/, &fFlushTLBs);
435 AssertLogRelRCReturnVoid(rc);
437 if (fFlushTLBs && rc != VINF_PGM_SYNC_CR3)
495 int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
496 if (RT_SUCCESS(rc))
511 AssertRC(rc);
550 int rc;
589 rc = pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs(pVM, pCur, pRam);
608 rc = VERR_PGM_HANDLER_PHYSICAL_CONFLICT;
613 rc = VERR_PGM_HANDLER_PHYSICAL_NO_RAM_RANGE;
619 rc = VERR_INVALID_PARAMETER;
635 rc = VERR_PGM_HANDLER_NOT_FOUND;
639 return rc;
660 int rc = VINF_SUCCESS;
675 rc = VERR_PGM_HANDLER_NOT_FOUND;
679 return rc;
699 int rc = MMHyperAlloc(pVM, sizeof(*pNew), 0, MM_TAG_PGM_HANDLERS, (void **)&pNew);
700 if (RT_FAILURE(rc))
701 return rc;
730 rc = VERR_PGM_PHYS_HANDLER_IPE;
735 rc = VERR_INVALID_PARAMETER;
741 rc = VERR_PGM_HANDLER_NOT_FOUND;
745 return rc;
762 int rc;
795 rc = VERR_PGM_PHYS_HANDLER_IPE;
800 rc = VERR_ACCESS_DENIED;
807 rc = VERR_INVALID_PARAMETER;
813 rc = VERR_PGM_HANDLER_NOT_FOUND;
819 rc = VERR_PGM_HANDLER_NOT_FOUND;
822 return rc;
849 int rc;
904 rc = pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs(pVM, pCur, pRam);
910 rc = VINF_SUCCESS;
919 rc = VERR_PGM_PHYS_HANDLER_IPE;
926 rc = VERR_PGM_HANDLER_NOT_FOUND;
930 return rc;
978 int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
979 AssertReturnStmt(RT_SUCCESS_NP(rc), pgmUnlock(pVM), rc);
1062 int rc = pgmPhysGetPageEx(pVM, GCPhysPageRemap, &pPageRemap);
1063 AssertReturnStmt(RT_SUCCESS_NP(rc), pgmUnlock(pVM), rc);
1069 rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1070 AssertReturnStmt(RT_SUCCESS_NP(rc), pgmUnlock(pVM), rc);
1180 int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1181 AssertReturnStmt(RT_SUCCESS_NP(rc), pgmUnlock(pVM), rc);
1431 int rc = pgmPhysGetPageWithHintEx(pVM, pPhys2Virt->Core.Key, &pPage, &pRamHint);
1432 if ( RT_SUCCESS(rc)
1436 AssertRC(rc);
1620 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, &fGst, &GCPhysGst);
1621 if ( rc == VERR_PAGE_NOT_PRESENT
1622 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
1633 AssertRCReturn(rc, 0);