Lines Matching refs:iPdpt
1642 * @param iPdpt Which PD entry to map (0..3).
1646 int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1653 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1654 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1655 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1669 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1674 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1676 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1680 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1681 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1684 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1691 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1692 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1694 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1696 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;