Lines Matching refs:pFpuCtx
5146 * @param pFpuCtx The FPU context.
5148 DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PIEMCPU pIemCpu, PCPUMCTX pCtx, PX86FXSTATE pFpuCtx)
5150 pFpuCtx->FOP = pIemCpu->abOpcode[pIemCpu->offFpuOpcode]
5157 pFpuCtx->CS = 0;
5158 pFpuCtx->FPUIP = pCtx->eip | ((uint32_t)pCtx->cs.Sel << 4);
5162 pFpuCtx->CS = pCtx->cs.Sel;
5163 pFpuCtx->FPUIP = pCtx->rip;
5173 * @param pFpuCtx The FPU context.
5177 DECLINLINE(void) iemFpuUpdateDP(PIEMCPU pIemCpu, PCPUMCTX pCtx, PX86FXSTATE pFpuCtx, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5192 /** @todo pFpuCtx->DS and FPUDP needs to be kept seperately. */
5195 pFpuCtx->DS = 0;
5196 pFpuCtx->FPUDP = (uint32_t)GCPtrEff | ((uint32_t)sel << 4);
5200 pFpuCtx->DS = sel;
5201 pFpuCtx->FPUDP = GCPtrEff;
5209 * @param pFpuCtx The FPU context.
5213 DECLINLINE(void) iemFpuRotateStackPush(PX86FXSTATE pFpuCtx)
5215 RTFLOAT80U r80Tmp = pFpuCtx->aRegs[7].r80;
5216 pFpuCtx->aRegs[7].r80 = pFpuCtx->aRegs[6].r80;
5217 pFpuCtx->aRegs[6].r80 = pFpuCtx->aRegs[5].r80;
5218 pFpuCtx->aRegs[5].r80 = pFpuCtx->aRegs[4].r80;
5219 pFpuCtx->aRegs[4].r80 = pFpuCtx->aRegs[3].r80;
5220 pFpuCtx->aRegs[3].r80 = pFpuCtx->aRegs[2].r80;
5221 pFpuCtx->aRegs[2].r80 = pFpuCtx->aRegs[1].r80;
5222 pFpuCtx->aRegs[1].r80 = pFpuCtx->aRegs[0].r80;
5223 pFpuCtx->aRegs[0].r80 = r80Tmp;
5230 * @param pFpuCtx The FPU context.
5234 DECLINLINE(void) iemFpuRotateStackPop(PX86FXSTATE pFpuCtx)
5236 RTFLOAT80U r80Tmp = pFpuCtx->aRegs[0].r80;
5237 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[1].r80;
5238 pFpuCtx->aRegs[1].r80 = pFpuCtx->aRegs[2].r80;
5239 pFpuCtx->aRegs[2].r80 = pFpuCtx->aRegs[3].r80;
5240 pFpuCtx->aRegs[3].r80 = pFpuCtx->aRegs[4].r80;
5241 pFpuCtx->aRegs[4].r80 = pFpuCtx->aRegs[5].r80;
5242 pFpuCtx->aRegs[5].r80 = pFpuCtx->aRegs[6].r80;
5243 pFpuCtx->aRegs[6].r80 = pFpuCtx->aRegs[7].r80;
5244 pFpuCtx->aRegs[7].r80 = r80Tmp;
5254 * @param pFpuCtx The FPU context.
5256 static void iemFpuMaybePushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, PX86FXSTATE pFpuCtx)
5259 uint16_t fFsw = pFpuCtx->FSW & ~X86_FSW_C_MASK;
5262 & ~(pFpuCtx->FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
5264 pFpuCtx->FSW = fFsw;
5269 if (!(pFpuCtx->FTW & RT_BIT(iNewTop)))
5272 pFpuCtx->FTW |= RT_BIT(iNewTop);
5273 pFpuCtx->aRegs[7].r80 = pResult->r80Result;
5275 else if (pFpuCtx->FCW & X86_FCW_IM)
5279 iemFpuStoreQNan(&pFpuCtx->aRegs[7].r80);
5284 pFpuCtx->FSW |= pResult->FSW & ~X86_FSW_C_MASK;
5285 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
5291 pFpuCtx->FSW = fFsw;
5293 iemFpuRotateStackPush(pFpuCtx);
5300 * @param pFpuCtx The FPU context.
5304 static void iemFpuStoreResultOnly(PX86FXSTATE pFpuCtx, PIEMFPURESULT pResult, uint8_t iStReg)
5307 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
5308 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5309 pFpuCtx->FSW |= pResult->FSW & ~X86_FSW_TOP_MASK;
5310 pFpuCtx->FTW |= RT_BIT(iReg);
5311 pFpuCtx->aRegs[iStReg].r80 = pResult->r80Result;
5319 * @param pFpuCtx The FPU context.
5322 static void iemFpuUpdateFSWOnly(PX86FXSTATE pFpuCtx, uint16_t u16FSW)
5324 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5325 pFpuCtx->FSW |= u16FSW & ~X86_FSW_TOP_MASK;
5332 * @param pFpuCtx The FPU context.
5334 static void iemFpuMaybePopOne(PX86FXSTATE pFpuCtx)
5337 uint16_t uFSW = pFpuCtx->FSW;
5338 if ( (pFpuCtx->FSW & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
5339 & ~(pFpuCtx->FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
5346 pFpuCtx->FSW = uFSW;
5350 pFpuCtx->FTW &= ~RT_BIT(iOldTop);
5353 iemFpuRotateStackPop(pFpuCtx);
5366 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5367 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5368 iemFpuMaybePushResult(pIemCpu, pResult, pFpuCtx);
5384 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5385 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5386 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5387 iemFpuMaybePushResult(pIemCpu, pResult, pFpuCtx);
5401 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5402 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5405 uint16_t fFsw = pFpuCtx->FSW & ~X86_FSW_C_MASK;
5408 & ~(pFpuCtx->FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
5410 pFpuCtx->FSW = fFsw;
5415 if (!(pFpuCtx->FTW & RT_BIT(iNewTop)))
5418 pFpuCtx->FTW |= RT_BIT(iNewTop);
5419 pFpuCtx->aRegs[0].r80 = pResult->r80Result1;
5420 pFpuCtx->aRegs[7].r80 = pResult->r80Result2;
5422 else if (pFpuCtx->FCW & X86_FCW_IM)
5426 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
5427 iemFpuStoreQNan(&pFpuCtx->aRegs[7].r80);
5432 pFpuCtx->FSW |= pResult->FSW & ~X86_FSW_C_MASK;
5433 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
5439 pFpuCtx->FSW = fFsw;
5441 iemFpuRotateStackPush(pFpuCtx);
5457 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5458 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5459 iemFpuStoreResultOnly(pFpuCtx, pResult, iStReg);
5475 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5476 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5477 iemFpuStoreResultOnly(pFpuCtx, pResult, iStReg);
5478 iemFpuMaybePopOne(pFpuCtx);
5496 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5497 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5498 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5499 iemFpuStoreResultOnly(pFpuCtx, pResult, iStReg);
5518 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5519 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5520 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5521 iemFpuStoreResultOnly(pFpuCtx, pResult, iStReg);
5522 iemFpuMaybePopOne(pFpuCtx);
5534 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5535 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5548 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5549 uint8_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
5550 pFpuCtx->FTW &= ~RT_BIT(iReg);
5561 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5562 uint16_t uFsw = pFpuCtx->FSW;
5567 pFpuCtx->FSW = uFsw;
5578 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5579 uint16_t uFsw = pFpuCtx->FSW;
5584 pFpuCtx->FSW = uFsw;
5597 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5598 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5599 iemFpuUpdateFSWOnly(pFpuCtx, u16FSW);
5612 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5613 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5614 iemFpuUpdateFSWOnly(pFpuCtx, u16FSW);
5615 iemFpuMaybePopOne(pFpuCtx);
5630 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5631 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5632 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5633 iemFpuUpdateFSWOnly(pFpuCtx, u16FSW);
5646 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5647 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5648 iemFpuUpdateFSWOnly(pFpuCtx, u16FSW);
5649 iemFpuMaybePopOne(pFpuCtx);
5650 iemFpuMaybePopOne(pFpuCtx);
5665 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5666 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5667 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5668 iemFpuUpdateFSWOnly(pFpuCtx, u16FSW);
5669 iemFpuMaybePopOne(pFpuCtx);
5677 * @param pFpuCtx The FPU context.
5680 static void iemFpuStackUnderflowOnly(PIEMCPU pIemCpu, PX86FXSTATE pFpuCtx, uint8_t iStReg)
5683 if (pFpuCtx->FCW & X86_FCW_IM)
5686 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5687 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
5688 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
5691 pFpuCtx->FTW |= RT_BIT(iReg);
5692 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
5697 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5698 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
5714 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5715 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5716 iemFpuStackUnderflowOnly(pIemCpu, pFpuCtx, iStReg);
5724 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5725 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5726 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5727 iemFpuStackUnderflowOnly(pIemCpu, pFpuCtx, iStReg);
5734 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5735 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5736 iemFpuStackUnderflowOnly(pIemCpu, pFpuCtx, iStReg);
5737 iemFpuMaybePopOne(pFpuCtx);
5745 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5746 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5747 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5748 iemFpuStackUnderflowOnly(pIemCpu, pFpuCtx, iStReg);
5749 iemFpuMaybePopOne(pFpuCtx);
5756 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5757 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5758 iemFpuStackUnderflowOnly(pIemCpu, pFpuCtx, UINT8_MAX);
5759 iemFpuMaybePopOne(pFpuCtx);
5760 iemFpuMaybePopOne(pFpuCtx);
5768 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5769 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5771 if (pFpuCtx->FCW & X86_FCW_IM)
5774 uint16_t iNewTop = (X86_FSW_TOP_GET(pFpuCtx->FSW) + 7) & X86_FSW_TOP_SMASK;
5775 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
5776 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
5777 pFpuCtx->FSW |= iNewTop << X86_FSW_TOP_SHIFT;
5778 pFpuCtx->FTW |= RT_BIT(iNewTop);
5779 iemFpuStoreQNan(&pFpuCtx->aRegs[7].r80);
5780 iemFpuRotateStackPush(pFpuCtx);
5785 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5786 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
5795 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5796 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5798 if (pFpuCtx->FCW & X86_FCW_IM)
5801 uint16_t iNewTop = (X86_FSW_TOP_GET(pFpuCtx->FSW) + 7) & X86_FSW_TOP_SMASK;
5802 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
5803 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
5804 pFpuCtx->FSW |= iNewTop << X86_FSW_TOP_SHIFT;
5805 pFpuCtx->FTW |= RT_BIT(iNewTop);
5806 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
5807 iemFpuStoreQNan(&pFpuCtx->aRegs[7].r80);
5808 iemFpuRotateStackPush(pFpuCtx);
5813 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5814 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
5822 * @param pFpuCtx The FPU context.
5824 static void iemFpuStackPushOverflowOnly(PX86FXSTATE pFpuCtx)
5826 if (pFpuCtx->FCW & X86_FCW_IM)
5829 uint16_t iNewTop = (X86_FSW_TOP_GET(pFpuCtx->FSW) + 7) & X86_FSW_TOP_SMASK;
5830 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
5831 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
5832 pFpuCtx->FSW |= iNewTop << X86_FSW_TOP_SHIFT;
5833 pFpuCtx->FTW |= RT_BIT(iNewTop);
5834 iemFpuStoreQNan(&pFpuCtx->aRegs[7].r80);
5835 iemFpuRotateStackPush(pFpuCtx);
5840 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
5841 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
5854 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5855 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5856 iemFpuStackPushOverflowOnly(pFpuCtx);
5871 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
5872 iemFpuUpdateDP(pIemCpu, pCtx, pFpuCtx, iEffSeg, GCPtrEff);
5873 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
5874 iemFpuStackPushOverflowOnly(pFpuCtx);
5880 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5881 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
5882 if (pFpuCtx->FTW & RT_BIT(iReg))
5890 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5891 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
5892 if (pFpuCtx->FTW & RT_BIT(iReg))
5894 *ppRef = &pFpuCtx->aRegs[iStReg].r80;
5904 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5905 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
5908 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
5910 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
5911 *ppRef1 = &pFpuCtx->aRegs[iStReg1].r80;
5920 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87;
5921 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
5924 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
5926 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
5936 * @param pFpuCtx The FPU context.
5938 static void iemFpuRecalcExceptionStatus(PX86FXSTATE pFpuCtx)
5940 uint16_t u16Fsw = pFpuCtx->FSW;
5941 if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pFpuCtx->FCW & X86_FCW_XCPT_MASK))
5945 pFpuCtx->FSW = u16Fsw;
5953 * @param pFpuCtx The FPU context.
5955 static uint16_t iemFpuCalcFullFtw(PCX86FXSTATE pFpuCtx)
5957 uint8_t const u8Ftw = (uint8_t)pFpuCtx->FTW;
5959 unsigned const iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
5968 PCRTFLOAT80U const pr80Reg = &pFpuCtx->aRegs[iSt].r80;
10500 PCX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
10512 pFpuCtx->FSW, pFpuCtx->FCW, pFpuCtx->FTW, pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK,