Lines Matching defs:ss
148 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
252 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
435 return pVCpu->cpum.s.Hyper.ss.Sel;
840 VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
842 pVCpu->cpum.s.Guest.ss.Sel = ss;
936 return pVCpu->cpum.s.Guest.ss.Sel;
2368 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2385 if ( pCtx->ss.Sel
2386 && (pCtx->ss.Sel & X86_SEL_RPL) == 0
2397 pCtx->ss.Sel |= 1;
2407 && (pCtx->ss.Sel & X86_SEL_RPL) == 1)
2410 pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 2;
2415 AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) >= 2 || pCtx->eflags.Bits.u1VM,
2429 ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL));
2462 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL));
2463 AssertMsg(pCtx->eflags.Bits.u1VM || pCtx->eflags.Bits.u2IOPL < (unsigned)(pCtx->ss.Sel & X86_SEL_RPL),
2464 ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL));
2469 if ( (pCtx->ss.Sel & X86_SEL_RPL) == 1
2490 pCtx->ss.Sel &= ~X86_SEL_RPL;
2504 && (pCtx->ss.Sel & X86_SEL_RPL) == 2)
2520 pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 1;
2733 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2759 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
2760 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
2763 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);