Lines Matching defs:State
419 TSTRTR0TIMERS1 State;
445 int rc = RTTimerCreateEx(&pTimer, 0, fFlags, tstRTR0TimerCallbackU32Counter, &State);
455 RT_ZERO(State); ASMAtomicWriteU32(&State.cShots, State.cShots);
457 for (uint32_t i = 0; i < 1000 && !ASMAtomicUoReadU32(&State.cShots); i++)
459 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 1, ("cShots=%u\n", State.cShots));
462 RT_ZERO(State); ASMAtomicWriteU32(&State.cShots, State.cShots);
464 for (uint32_t i = 0; i < 1000 && !ASMAtomicUoReadU32(&State.cShots); i++)
466 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 1, ("cShots=%u\n", State.cShots));
469 RT_ZERO(State); ASMAtomicWriteU32(&State.cShots, State.cShots);
473 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 0, ("cShots=%u\n", State.cShots));
476 RT_ZERO(State); ASMAtomicWriteU32(&State.cShots, State.cShots);
482 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 0, ("cShots=%u\n", State.cShots));
498 int rc = RTTimerCreateEx(&pTimer, 0, fFlags, tstRTR0TimerCallbackRestartOnce, &State);
506 RT_ZERO(State);
507 State.iActionShot = 0;
508 ASMAtomicWriteU32(&State.cShots, State.cShots);
512 for (uint32_t i = 0; i < 1000 && ASMAtomicUoReadU32(&State.cShots) < 2; i++)
514 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 2, ("cShots=%u\n", State.cShots));
531 int rc = RTTimerCreateEx(&pTimer, 0, fFlags, tstRTR0TimerCallbackDestroyOnce, &State);
539 RT_ZERO(State);
540 State.rc = VERR_IPE_UNINITIALIZED_STATUS;
541 State.iActionShot = 0;
542 ASMAtomicWriteU32(&State.cShots, State.cShots);
546 for (uint32_t i = 0; i < 1000 && (ASMAtomicUoReadU32(&State.cShots) < 1 || State.rc == VERR_IPE_UNINITIALIZED_STATUS); i++)
548 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicReadU32(&State.cShots) == 1, ("cShots=%u\n", State.cShots));
549 RTR0TESTR0_CHECK_MSG_BREAK(State.rc == VINF_SUCCESS, ("rc=%Rrc\n", State.rc));
551 if (RT_FAILURE(State.rc))
567 RT_ZERO(State);
568 State.iActionShot = 0;
569 State.rc = VINF_SUCCESS;
570 State.u.Specific.idCpu = RTMpCpuIdFromSetIndex(iCpu);
571 ASMAtomicWriteU32(&State.cShots, State.cShots);
575 int rc = RTTimerCreateEx(&pTimer, 0, fFlags, tstRTR0TimerCallbackSpecific, &State);
585 ASMAtomicWriteU32(&State.cShots, 0);
588 for (uint32_t j = 0; j < 1000 && ASMAtomicUoReadU32(&State.cShots) < 1; j++)
591 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicReadU32(&State.cShots) == 1,
593 State.cShots, iCpu, i, RTMpCpuIdToSetIndex(RTMpCpuId()), cNsElapsed ));
594 RTR0TESTR0_CHECK_MSG_BREAK(State.rc == VINF_SUCCESS, ("rc=%Rrc\n", State.rc));
595 RTR0TESTR0_CHECK_MSG_BREAK(!State.u.Specific.fFailed, ("iCpu=%u i=%u\n", iCpu, i));
618 RTR0TESTR0_CHECK_RC_BREAK(RTTimerCreateEx(&pTimer, u10HzAsNs, fFlags, tstRTR0TimerCallbackU32Counter, &State),
623 RT_ZERO(State);
624 State.fPeriodic = true;
625 ASMAtomicWriteU32(&State.cShots, State.cShots);
629 for (uint32_t i = 0; i < 1000 && ASMAtomicUoReadU32(&State.cShots) < 10; i++)
632 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicUoReadU32(&State.cShots) == 10, ("cShots=%u\n", State.cShots));
633 if (tstRTR0TimerCheckShotIntervals(&State, uStartNsTS, u10HzAsNsMin, u10HzAsNsMax))
649 RTR0TESTR0_CHECK_RC_BREAK(RTTimerCreateEx(&pTimer, cNsSysHz, fFlags, tstRTR0TimerCallbackU32Counter, &State),
653 RT_ZERO(State);
654 State.fPeriodic = true;
655 ASMAtomicWriteU32(&State.cShots, State.cShots); /* ordered, necessary? */
658 for (uint32_t k = 0; k < 1000 && ASMAtomicUoReadU32(&State.cShots) < 2; k++)
671 RT_ZERO(State);
672 State.cShots = 0;
673 State.rc = VERR_IPE_UNINITIALIZED_STATUS;
674 State.iActionShot = 42;
675 State.fPeriodic = true;
676 State.u.ChgInt.fDirection = !!(u64Arg & 1);
679 State.u.ChgInt.cNsMaxInterval = RT_MAX(cNsMaxHighResHz * 10, 20000000); /* 10x / 20 ms */
680 State.u.ChgInt.cNsMinInterval = RT_MAX(cNsMaxHighResHz, 10000); /* min / 10 us */
684 State.u.ChgInt.cNsMaxInterval = cNsSysHz * 4;
685 State.u.ChgInt.cNsMinInterval = cNsSysHz;
687 State.u.ChgInt.cNsChangeStep = (State.u.ChgInt.cNsMaxInterval - State.u.ChgInt.cNsMinInterval) / 10;
688 State.u.ChgInt.cNsCurInterval = State.u.ChgInt.fDirection
689 ? State.u.ChgInt.cNsMaxInterval : State.u.ChgInt.cNsMinInterval;
690 State.u.ChgInt.cStepsBetween = u64Arg & 4 ? 1 : 3;
691 RTR0TESTR0_CHECK_MSG_BREAK(State.u.ChgInt.cNsMinInterval > 1000, ("%u\n", State.u.ChgInt.cNsMinInterval));
692 RTR0TESTR0_CHECK_MSG_BREAK(State.u.ChgInt.cNsMaxInterval > State.u.ChgInt.cNsMinInterval, ("max=%u min=%u\n", State.u.ChgInt.cNsMaxInterval, State.u.ChgInt.cNsMinInterval));
693 ASMAtomicWriteU32(&State.cShots, State.cShots);
698 RTR0TESTR0_CHECK_RC_BREAK(RTTimerCreateEx(&pTimer, cNsSysHz, fFlags, tstRTR0TimerCallbackChangeInterval, &State),
700 int rc = RTTimerChangeInterval(pTimer, State.u.ChgInt.cNsMinInterval);
709 RTR0TESTR0_CHECK_RC_BREAK(RTTimerStart(pTimer, u64Arg & 2 ? State.u.ChgInt.cNsCurInterval : 0), VINF_SUCCESS);
712 && ASMAtomicReadU32(&State.cShots) <= State.iActionShot
713 && State.rc == VERR_IPE_UNINITIALIZED_STATUS;
732 RT_ZERO(State);
733 State.iActionShot = 0;
734 State.rc = VINF_SUCCESS;
735 State.fPeriodic = true;
736 State.u.Specific.idCpu = RTMpCpuIdFromSetIndex(iCpu);
737 ASMAtomicWriteU32(&State.cShots, State.cShots);
741 int rc = RTTimerCreateEx(&pTimer, cNsSysHz, fFlags, tstRTR0TimerCallbackSpecific, &State);
751 ASMAtomicWriteU32(&State.cShots, 0);
754 for (uint32_t j = 0; j < 1000 && ASMAtomicUoReadU32(&State.cShots) < 8; j++)
758 RTR0TESTR0_CHECK_MSG_BREAK(ASMAtomicReadU32(&State.cShots) > 5,
760 State.cShots, iCpu, i, RTMpCpuIdToSetIndex(RTMpCpuId()), cNsElapsed));
761 RTR0TESTR0_CHECK_MSG_BREAK(State.rc == VINF_SUCCESS, ("rc=%Rrc\n", State.rc));
762 RTR0TESTR0_CHECK_MSG_BREAK(!State.u.Specific.fFailed, ("iCpu=%u i=%u\n", iCpu, i));