Lines Matching refs:pState
29 #define INSTANCE(pState) pState->szInstance
70 void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
72 //Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
78 uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
82 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
88 uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
92 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
98 void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
102 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
111 PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
116 bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
118 if (vqueueIsEmpty(pState, pQueue))
121 Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122 QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
127 bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
129 if (vqueueIsEmpty(pState, pQueue))
134 Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135 QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
138 uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
146 vringReadDesc(pState, &pQueue->VRing, idx, &desc);
149 Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
150 QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
155 Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
156 QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
167 Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
168 QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
172 uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
175 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
181 void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
183 PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
188 void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
194 PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
199 void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
203 Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
204 QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
210 Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
211 QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
212 PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
220 Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
221 QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
222 vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
225 void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
228 INSTANCE(pState), QUEUENAME(pState, pQueue),
229 vringReadAvailFlags(pState, &pQueue->VRing),
230 pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
231 if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
232 || ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
234 int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
236 Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
240 STAM_COUNTER_INC(&pState->StatIntsSkipped);
245 void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
247 Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
248 QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
249 vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
250 vqueueNotify(pState, pQueue);
253 void vpciReset(PVPCISTATE pState)
255 pState->uGuestFeatures = 0;
256 pState->uQueueSelector = 0;
257 pState->uStatus = 0;
258 pState->uISR = 0;
260 for (unsigned i = 0; i < pState->nQueues; i++)
261 vqueueReset(&pState->Queues[i]);
268 * @param pState The device state structure.
272 int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
274 // int rc = vpciCsEnter(pState, rcBusy);
278 STAM_COUNTER_INC(&pState->StatIntsRaised);
280 INSTANCE(pState), u8IntCause));
282 pState->uISR |= u8IntCause;
283 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
284 // vpciCsLeave(pState);
291 * @param pState The device state structure.
293 static void vpciLowerInterrupt(VPCISTATE *pState)
295 LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
296 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
299 DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
302 return pfnGetHostFeatures(pState)
326 VPCISTATE *pState = PDMINS_2_DATA(pDevIns, VPCISTATE *);
328 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
339 rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
342 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
346 Port -= pState->IOPortBase;
351 *pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
356 *pu32 = pState->uGuestFeatures;
360 *pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
365 *(uint16_t*)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
370 *(uint16_t*)pu32 = pState->uQueueSelector;
375 *(uint8_t*)pu32 = pState->uStatus;
380 *(uint8_t*)pu32 = pState->uISR;
381 pState->uISR = 0; /* read clears all interrupts */
382 vpciLowerInterrupt(pState);
387 rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
392 INSTANCE(pState), Port, cb);
396 Log3(("%s vpciIOPortIn: At %RTiop in %0*x\n", INSTANCE(pState), Port, cb*2, *pu32));
397 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
398 //vpciCsLeave(pState);
423 VPCISTATE *pState = PDMINS_2_DATA(pDevIns, VPCISTATE *);
426 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
428 Port -= pState->IOPortBase;
429 Log3(("%s virtioIOPortOut: At %RTiop out %0*x\n", INSTANCE(pState), Port, cb*2, u32));
438 INSTANCE(pState), u32));
439 pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
442 else if (~vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures) & u32)
445 INSTANCE(pState),
446 vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures), u32));
447 pState->uGuestFeatures =
448 vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
451 pState->uGuestFeatures = u32;
452 pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
462 pState->Queues[pState->uQueueSelector].uPageNumber = u32;
464 vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
466 rc = pCallbacks->pfnReset(pState);
472 if (u32 < pState->nQueues)
473 pState->uQueueSelector = u32;
475 Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
482 if (u32 < pState->nQueues)
483 if (pState->Queues[u32].VRing.addrDescriptors)
485 // rc = vpciCsEnter(pState, VERR_SEM_BUSY);
488 pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
489 // vpciCsLeave(pState);
494 INSTANCE(pState), u32));
496 Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
505 fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
506 pState->uStatus = u32;
509 rc = pCallbacks->pfnReset(pState);
511 pCallbacks->pfnReady(pState);
516 rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
519 INSTANCE(pState), Port, cb);
523 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
553 VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
558 *ppLed = &pState->led;
568 * @param pState Pointer to the device state structure.
571 void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
573 LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
575 pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
577 pState->led.Actual.s.fWriting = fOn;
584 * @param pState Pointer to the device state structure.
587 void vpciSetReadLed(PVPCISTATE pState, bool fOn)
589 LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
591 pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
593 pState->led.Actual.s.fReading = fOn;
637 static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
645 pState->uGuestFeatures,
646 pState->uQueueSelector,
647 pState->uStatus,
648 pState->uISR));
650 for (unsigned i = 0; i < pState->nQueues; i++)
659 pState->Queues[i].pcszName,
660 pState->Queues[i].VRing.uSize,
661 pState->Queues[i].VRing.addrDescriptors,
662 pState->Queues[i].VRing.addrAvail,
663 pState->Queues[i].VRing.addrUsed,
664 pState->Queues[i].uNextAvailIndex,
665 pState->Queues[i].uNextUsedIndex,
666 pState->Queues[i].uPageNumber));
679 int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
683 vpciDumpState(pState, "vpciSaveExec");
685 rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
687 rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
689 rc = SSMR3PutU8( pSSM, pState->uStatus);
691 rc = SSMR3PutU8( pSSM, pState->uISR);
695 rc = SSMR3PutU32(pSSM, pState->nQueues);
697 for (unsigned i = 0; i < pState->nQueues; i++)
699 rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
701 rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
703 rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
705 rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
721 int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
728 rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
730 rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
732 rc = SSMR3GetU8( pSSM, &pState->uStatus);
734 rc = SSMR3GetU8( pSSM, &pState->uISR);
740 rc = SSMR3GetU32(pSSM, &pState->nQueues);
744 pState->nQueues = nQueues;
745 for (unsigned i = 0; i < pState->nQueues; i++)
747 rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
749 rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
752 if (pState->Queues[i].uPageNumber)
753 vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
755 rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
757 rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
762 vpciDumpState(pState, "vpciLoadExec");
812 DECLCALLBACK(int) vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
818 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
821 pState->pDevInsR3 = pDevIns;
822 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
823 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
824 pState->led.u32Magic = PDMLED_MAGIC;
826 pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
829 int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
834 vpciConfigure(pState->pciDevice, uSubsystemId, uClass);
836 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
852 PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
859 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
862 pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
864 pState->nQueues = nQueues;
867 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
868 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
869 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
870 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
871 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
872 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
873 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
874 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
886 * @param pState The device state structure.
888 int vpciDestruct(VPCISTATE* pState)
890 Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
892 if (PDMCritSectIsInitialized(&pState->cs))
893 PDMR3CritSectDelete(&pState->cs);
916 VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
917 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
921 PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
925 for (unsigned i = 0; i < pState->nQueues; i++)
927 if (pState->Queues[i].VRing.uSize == 0)
929 pQueue = &pState->Queues[i];
936 Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));