Lines Matching defs:dma_chann
706 int dma_chann;
709 uint8_t dma_chann;
882 fdctrl->dor |= (fdctrl->dma_chann != 0xff) ? FD_DOR_DMAEN : 0;
1215 PDMDevHlpDMASetDREQ (fdctrl->pDevIns, fdctrl->dma_chann, 0);
1217 DMA_release_DREQ(fdctrl->dma_chann);
1313 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1315 dma_mode = PDMDevHlpDMAGetChannelMode (fdctrl->pDevIns, fdctrl->dma_chann);
1332 DMA_hold_DREQ(fdctrl->dma_chann);
1333 DMA_schedule(fdctrl->dma_chann);
1335 PDMDevHlpDMASetDREQ (fdctrl->pDevIns, fdctrl->dma_chann, 1);
1422 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1424 dma_mode = PDMDevHlpDMAGetChannelMode (fdctrl->pDevIns, fdctrl->dma_chann);
1438 DMA_hold_DREQ(fdctrl->dma_chann);
1439 DMA_schedule(fdctrl->dma_chann);
1441 PDMDevHlpDMASetDREQ (fdctrl->pDevIns, fdctrl->dma_chann, 1);
2830 uint8_t irq_lvl, dma_chann;
2848 rc = CFGMR3QueryU8Def(pCfg, "DMA", &dma_chann, 2);
2860 LogFlow(("fdcConstruct: irq_lvl=%d dma_chann=%d io_base=%#x\n", irq_lvl, dma_chann, io_base));
2864 pThis->dma_chann = dma_chann;
2902 if (pThis->dma_chann != 0xff)
2904 rc = PDMDevHlpDMARegister(pDevIns, dma_chann, &fdctrl_transfer_handler, pThis);