Lines Matching refs:RT_H2LE_U16
1213 p[0] = RT_H2LE_U16(0x0040);
1214 p[1] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1215 p[3] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1217 p[5] = RT_H2LE_U16(s->cbSector);
1218 p[6] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1220 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1221 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1222 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
1226 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
1228 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
1229 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1230 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1231 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1232 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1233 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
1234 p[54] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1235 p[55] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1236 p[56] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1237 p[57] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1240 p[58] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1244 p[59] = RT_H2LE_U16(0x100 | s->cMultSectors);
1247 p[60] = RT_H2LE_U16(s->cTotalSectors);
1248 p[61] = RT_H2LE_U16(s->cTotalSectors >> 16);
1253 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
1254 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
1256 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1257 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1258 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1259 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1260 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1261 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1266 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
1267 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
1271 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1272 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1274 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
1276 p[83] = RT_H2LE_U16(1 << 14 | 1 << 12); /* supports FLUSH CACHE */
1278 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1279 p[84] = RT_H2LE_U16(1 << 14);
1280 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
1282 p[86] = RT_H2LE_U16(1 << 12); /* enabled FLUSH CACHE */
1284 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1285 p[87] = RT_H2LE_U16(1 << 14);
1286 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1287 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1290 p[100] = RT_H2LE_U16(s->cTotalSectors);
1291 p[101] = RT_H2LE_U16(s->cTotalSectors >> 16);
1292 p[102] = RT_H2LE_U16(s->cTotalSectors >> 32);
1293 p[103] = RT_H2LE_U16(s->cTotalSectors >> 48);
1300 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
1301 p[117] = RT_H2LE_U16(cSectorSizeInWords);
1302 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
1306 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
1308 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
1310 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1349 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 0 << 5 | 0 << 0);
1351 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1352 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1355 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1356 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1357 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1358 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1359 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
1360 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1361 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1362 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1363 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1364 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1365 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1366 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
1367 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
1368 p[75] = RT_H2LE_U16(1); /* queue depth 1 */
1369 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1370 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1371 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
1372 p[83] = RT_H2LE_U16(1 << 14);
1373 p[84] = RT_H2LE_U16(1 << 14);
1374 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
1375 p[86] = RT_H2LE_U16(0);
1376 p[87] = RT_H2LE_U16(1 << 14);
1377 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1378 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1393 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */