Lines Matching defs:uAsyncIOState

388     uint8_t     uAsyncIOState;
847 fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW);
883 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegCommand, pCtl->uAsyncIOState));
5112 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->uAsyncIOState, ReqType));
5113 if (pCtl->uAsyncIOState != ReqType)
5118 if ( (pCtl->uAsyncIOState == ATA_AIO_PIO || pCtl->uAsyncIOState == ATA_AIO_DMA)
5124 AssertReleaseMsg(ReqType == ATA_AIO_RESET_ASSERTED || ReqType == ATA_AIO_RESET_CLEARED || ReqType == ATA_AIO_ABORT || pCtl->uAsyncIOState == ReqType, ("I/O state inconsistent: state=%d request=%d\n", pCtl->uAsyncIOState, ReqType));
5134 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
5219 * important: do not change uAsyncIOState. */
5229 pCtl->uAsyncIOState = ATA_AIO_DMA;
5243 pCtl->uAsyncIOState = ATA_AIO_NEW;
5259 pCtl->uAsyncIOState = ATA_AIO_PIO;
5271 pCtl->uAsyncIOState = ATA_AIO_NEW;
5282 pCtl->uAsyncIOState = ATA_AIO_NEW;
5339 pCtl->uAsyncIOState = ATA_AIO_NEW;
5372 * Most important: do not change uAsyncIOState. */
5385 pCtl->uAsyncIOState = ATA_AIO_PIO;
5397 pCtl->uAsyncIOState = ATA_AIO_NEW;
5410 pCtl->uAsyncIOState = ATA_AIO_NEW;
5415 pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED;
5424 pCtl->uAsyncIOState = ATA_AIO_NEW;
5448 pCtl->uAsyncIOState = ATA_AIO_NEW;
5469 AssertMsgFailed(("Undefined async I/O state %d\n", pCtl->uAsyncIOState));
5475 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
6491 SSMR3PutU8(pSSM, pThis->aCts[i].uAsyncIOState);
6664 SSMR3GetU8(pSSM, &pThis->aCts[i].uAsyncIOState);
7409 pCtl->uAsyncIOState = ATA_AIO_NEW;