3036     p[0] = RT_H2LE_U16(0x0040);
3037     p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
3038     p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
3040     p[5] = RT_H2LE_U16(512);
3041     p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
3043     p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3044     p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3045     p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
3049     p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
3051     p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
3052     p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3053     p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
3054     p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3055     p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3056     p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
3057     p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
3058     p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
3059     p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
3060     p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
3061     p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
3063         p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
3066         p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
3067         p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
3072         p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
3073         p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
3075     p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3076     p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3077     p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3078     p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3079     p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3080     p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3087         p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
3088         p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
3092         p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3093         p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3095     p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management,  write cache and look-ahead */
3096     p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
3097     p[84] = RT_H2LE_U16(1 << 14);
3098     p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management,  write cache and look-ahead */
3099     p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
3100     p[87] = RT_H2LE_U16(1 << 14);
3101     p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3102     p[93] = RT_H2LE_U16(0x00);
3103     p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
3104     p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
3105     p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
3106     p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
3110         p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
3116         p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
3117         p[117] = RT_H2LE_U16(cSectorSizeInWords);
3118         p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
3122         p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
3127         p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
3130     p[75] = RT_H2LE_U16(pAhciPort->CTX_SUFF(pAhci)->cCmdSlotsAvail-1); /* Number of commands we support, 0's based */
3131     p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
3134     p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
3214     p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
3216     p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3217     p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3220     p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3221     p[50] = RT_H2LE_U16(1 << 14);  /* No drive specific standby timer minimum */
3222     p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3223     p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3224     p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
3225     p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3226     p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3227     p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3228     p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3229     p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3230     p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3231     p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
3232     p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
3233     p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3234     p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3235     p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
3236     p[83] = RT_H2LE_U16(1 << 14);
3237     p[84] = RT_H2LE_U16(1 << 14);
3238     p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
3239     p[86] = RT_H2LE_U16(0);
3240     p[87] = RT_H2LE_U16(1 << 14);
3241     p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3242     p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
3245     p[75] = RT_H2LE_U16(31); /* We support 32 commands */
3246     p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */

Indexes created Tue Jul 24 14:28:13 CEST 2018