Lines Matching defs:chidx

89  * while 'chidx' refers to a DMA channel index within a controller (0-3).
239 int chidx, reg, is_count;
243 chidx = reg >> 1;
245 ch = &dc->ChState[chidx];
265 Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
266 port, chidx, u32));
283 int chidx, reg, val, dir;
287 chidx = reg >> 1;
288 ch = &dc->ChState[chidx];
314 int chidx = 0;
332 chidx = u32 & 3;
334 dc->u8Status |= 1 << (chidx + 4);
336 dc->u8Status &= ~(1 << (chidx + 4));
337 dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
340 chidx = u32 & 3;
342 dc->u8Mask |= 1 << chidx;
344 dc->u8Mask &= ~(1 << chidx);
350 chidx = u32 & 3;
353 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
354 chidx, op, IS_MODE_AI(u32) ? "" : "no ",
357 dc->ChState[chidx].u8Mode = u32;
376 Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
377 port, chidx, u32));
546 static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
549 DMAChannel *ch = &dc->ChState[chidx];
564 end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
574 dc->u8Status |= RT_BIT(chidx);
575 Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
590 int ctlidx, chidx, mask;
602 for (chidx = 0; chidx < 4; ++chidx)
604 mask = 1 << chidx;
606 dmaRunChannel(pThis, ctlidx, chidx);
753 int chidx;
758 chidx = uChannel & 3;
760 dc->u8Status |= 1 << (chidx + 4);
762 dc->u8Status &= ~(1 << (chidx + 4));
830 int chidx;
844 for (chidx = 0; chidx < 4; ++chidx)
846 DMAChannel *ch = &dc->ChState[chidx];
860 int chidx;
876 for (chidx = 0; chidx < 4; ++chidx)
878 DMAChannel *ch = &dc->ChState[chidx];
901 dc->au8Page[DMACX2PG(chidx)] = u8val;
903 dc->au8PageHi[DMACX2PG(chidx)] = u8val;