Lines Matching refs:pDev
5 * @remarks This code does not use pThis, it uses pDev and pApic due to the
348 * @remarks This is generally pointed to by a parameter or variable named pDev.
409 static void apic_update_tpr(APICDeviceInfo *pDev, APICState *pApic, uint32_t val);
411 static void apic_eoi(APICDeviceInfo *pDev, APICState *pApic); /* */
412 static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo *pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet);
413 static int apic_deliver(APICDeviceInfo *pDev, APICState *pApic,
419 static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *pApic);
420 static void apicTimerSetInitialCount(APICDeviceInfo *pDev, APICState *pApic, uint32_t initial_count);
421 static void apicTimerSetLvt(APICDeviceInfo *pDev, APICState *pApic, uint32_t fNew);
422 static void apicSendInitIpi(APICDeviceInfo *pDev, APICState *pApic);
424 static void apicR3InitIpi(APICDeviceInfo *pDev, APICState *pApic);
425 static void apic_set_irq(APICDeviceInfo *pDev, APICState *pApic, int vector_num, int trigger_mode, uint32_t uTagSrc);
426 static bool apic_update_irq(APICDeviceInfo *pDev, APICState *pApic);
429 DECLINLINE(APICState *) apicGetStateById(APICDeviceInfo *pDev, VMCPUID id)
431 AssertFatalMsg(id < pDev->cCpus, ("CPU id %d out of range\n", id));
432 return &pDev->CTX_SUFF(paLapics)[id];
438 DECLINLINE(APICState *) apicGetStateByCurEmt(APICDeviceInfo *pDev)
441 VMCPUID id = pDev->CTX_SUFF(pApicHlp)->pfnGetCpuId(pDev->CTX_SUFF(pDevIns));
442 return apicGetStateById(pDev, id);
445 DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo *pDev, APICState *pApic)
451 DECLINLINE(void) apicCpuSetInterrupt(APICDeviceInfo *pDev, APICState *pApic, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
453 LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(pDev, pApic)));
454 pDev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
455 getCpuFromLapic(pDev, pApic));
458 DECLINLINE(void) apicCpuClearInterrupt(APICDeviceInfo *pDev, APICState *pApic, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
461 pDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
462 getCpuFromLapic(pDev, pApic));
467 DECLINLINE(void) apicR3CpuSendSipi(APICDeviceInfo *pDev, APICState *pApic, int vector)
471 pDev->pApicHlpR3->pfnSendSipi(pDev->pDevInsR3,
472 getCpuFromLapic(pDev, pApic),
476 DECLINLINE(void) apicR3CpuSendInitIpi(APICDeviceInfo *pDev, APICState *pApic)
480 pDev->pApicHlpR3->pfnSendInitIpi(pDev->pDevInsR3,
481 getCpuFromLapic(pDev, pApic));
486 DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo *pDev)
488 switch (pDev->enmVersion)
497 AssertMsgFailed(("Unsupported APIC version %d\n", pDev->enmVersion));
519 static int apic_bus_deliver(APICDeviceInfo *pDev,
534 APICState *pApic = apicGetStateById(pDev, idDstCpu);
535 apic_set_irq(pDev, pApic, vector_num, trigger_mode, uTagSrc);
545 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
546 apicCpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_SMI);
551 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
552 apicCpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_NMI);
559 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
560 apicSendInitIpi(pDev, pCurApic);
576 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
577 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode, uTagSrc);
585 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
586 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
587 APICState *pApic = apicGetStateById(pDev, idCpu);
591 /* APIC_LOCK_VOID(pDev, VERR_INTERNAL_ERROR); */
596 | (val & getApicEnableBits(pDev)) /* mode */
608 apicCpuClearInterrupt(pDev, pApic);
614 pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
629 /* APIC_UNLOCK(pDev); */
634 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
635 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
636 APICState *pApic = apicGetStateById(pDev, idCpu);
643 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
644 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
645 APICState *pApic = apicGetStateById(pDev, idCpu);
647 apic_update_tpr(pDev, pApic, val);
653 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
654 APICState *pApic = apicGetStateById(pDev, idCpu);
662 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
663 APICState *pApic = apicGetStateById(pDev, 0);
674 * @param pDev The PDM device instance.
682 static int apicWriteRegisterInvalid(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
686 int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
688 APIC_LOCK(pDev, rcBusy);
690 APIC_UNLOCK(pDev);
700 * @param pDev The PDM device instance.
708 static int apicWriteRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
711 Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
717 APIC_LOCK(pDev, rcBusy);
719 APIC_UNLOCK(pDev);
727 APIC_LOCK(pDev, rcBusy);
728 apic_update_tpr(pDev, pApic, u64Value);
729 APIC_UNLOCK(pDev);
737 APIC_LOCK(pDev, rcBusy);
738 apic_eoi(pDev, pApic);
739 APIC_UNLOCK(pDev);
743 APIC_LOCK(pDev, rcBusy);
745 APIC_UNLOCK(pDev);
749 APIC_LOCK(pDev, rcBusy);
751 APIC_UNLOCK(pDev);
755 APIC_LOCK(pDev, rcBusy);
757 apic_update_irq(pDev, pApic);
758 APIC_UNLOCK(pDev);
769 APIC_LOCK(pDev, rcBusy);
773 rc = apic_deliver(pDev, pApic, (pApic->icr[1] >> 24) & 0xff, (pApic->icr[0] >> 11) & 1,
776 APIC_UNLOCK(pDev);
782 APIC_LOCK(pDev, rcBusy);
784 APIC_UNLOCK(pDev);
787 rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
792 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
793 apicTimerSetLvt(pDev, pApic, u64Value);
794 APIC_AND_TM_UNLOCK(pDev, pApic);
798 APIC_LOCK(pDev, rcBusy);
800 APIC_UNLOCK(pDev);
804 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
805 apicTimerSetInitialCount(pDev, pApic, u64Value);
806 APIC_AND_TM_UNLOCK(pDev, pApic);
815 APIC_LOCK(pDev, rcBusy);
819 APIC_UNLOCK(pDev);
827 APIC_LOCK(pDev, rcBusy);
832 rc = apic_bus_deliver(pDev,
838 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
839 APIC_UNLOCK(pDev);
845 rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
857 * @param pDev The PDM device instance.
865 static int apicReadRegisterInvalid(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t *pu64Value,
869 int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
871 APIC_LOCK(pDev, rcBusy);
873 APIC_UNLOCK(pDev);
883 * @param pDev The PDM device instance.
891 static int apicReadRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t *pu64Value,
894 Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
900 APIC_LOCK(pDev, rcBusy);
902 APIC_UNLOCK(pDev);
906 APIC_LOCK(pDev, rcBusy);
913 APIC_UNLOCK(pDev);
917 APIC_LOCK(pDev, rcBusy);
919 APIC_UNLOCK(pDev);
928 APIC_LOCK(pDev, rcBusy);
930 APIC_UNLOCK(pDev);
939 APIC_LOCK(pDev, rcBusy);
941 APIC_UNLOCK(pDev);
946 APIC_LOCK(pDev, rcBusy);
948 APIC_UNLOCK(pDev);
952 APIC_LOCK(pDev, rcBusy);
954 APIC_UNLOCK(pDev);
958 APIC_LOCK(pDev, rcBusy);
960 APIC_UNLOCK(pDev);
964 APIC_LOCK(pDev, rcBusy);
966 APIC_UNLOCK(pDev);
970 APIC_LOCK(pDev, rcBusy);
972 APIC_UNLOCK(pDev);
976 APIC_LOCK(pDev, rcBusy);
978 APIC_UNLOCK(pDev);
983 APIC_LOCK(pDev, rcBusy);
988 APIC_UNLOCK(pDev);
993 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
996 APIC_LOCK(pDev, rcBusy);
998 APIC_UNLOCK(pDev);
1003 APIC_LOCK(pDev, rcBusy);
1005 APIC_UNLOCK(pDev);
1009 APIC_LOCK(pDev, rcBusy);
1011 APIC_UNLOCK(pDev);
1015 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
1016 *pu64Value = apic_get_current_count(pDev, pApic);
1017 APIC_AND_TM_UNLOCK(pDev, pApic);
1021 APIC_LOCK(pDev, rcBusy);
1023 APIC_UNLOCK(pDev);
1034 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1042 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1053 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1054 if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1057 APICState *pApic = apicGetStateById(pDev, idCpu);
1059 return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
1068 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1070 if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1073 APICState *pApic = apicGetStateById(pDev, idCpu);
1075 return apicReadRegister(pDev, pApic, iReg, pu64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
1086 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1087 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1091 return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode, &DstSet),
1101 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1102 APICState *pApic = apicGetStateById(pDev, 0);
1104 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1112 apicCpuSetInterrupt(pDev, pApic, PDMAPICIRQ_EXTINT);
1114 apicCpuClearInterrupt(pDev, pApic, PDMAPICIRQ_EXTINT);
1145 apicCpuSetInterrupt(pDev, pApic, enmType);
1147 apicCpuClearInterrupt(pDev, pApic, enmType);
1178 apicCpuSetInterrupt(pDev, pApic, enmType);
1209 static bool apic_update_irq(APICDeviceInfo *pDev, APICState *pApic)
1214 apicCpuClearInterrupt(pDev, pApic);
1224 apicCpuSetInterrupt(pDev, pApic);
1231 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1232 if (!pDev)
1237 APICState *pApic = apicGetStateById(pDev, idCpu);
1261 static void apic_update_tpr(APICDeviceInfo *pDev, APICState *pApic, uint32_t val)
1266 fIrqWasActive = apic_update_irq(pDev, pApic);
1268 fIrqIsActive = apic_update_irq(pDev, pApic);
1274 STAM_COUNTER_INC(&pDev->StatClearedActiveIrq);
1275 apicCpuClearInterrupt(pDev, pApic);
1279 static void apic_set_irq(APICDeviceInfo *pDev, APICState *pApic, int vector_num, int trigger_mode, uint32_t uTagSrc)
1294 apic_update_irq(pDev, pApic);
1297 static void apic_eoi(APICDeviceInfo *pDev, APICState *pApic)
1306 apic_update_irq(pDev, pApic);
1309 static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo *pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet)
1323 APIC_FOREACH_BEGIN(pDev);
1343 static void apicR3InitIpi(APICDeviceInfo *pDev, APICState *pApic)
1366 static void apicSendInitIpi(APICDeviceInfo *pDev, APICState *pApic)
1368 apicR3InitIpi(pDev, pApic);
1369 apicR3CpuSendInitIpi(pDev, pApic);
1373 static void apicR3Startup(APICDeviceInfo *pDev, APICState *pApic, int vector_num)
1376 apicR3CpuSendSipi(pDev, pApic, vector_num);
1381 static int apic_deliver(APICDeviceInfo *pDev, APICState *pApic,
1393 apic_get_delivery_bitmask(pDev, dest, dest_mode, &DstSet);
1416 APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1427 APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1428 apicR3Startup(pDev, pCurApic, vector_num);
1438 return apic_bus_deliver(pDev, &DstSet, delivery_mode, vector_num,
1440 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
1446 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1448 if (!pDev)
1450 Log(("apic_get_interrupt: returns -1 (!pDev)\n"));
1454 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1456 APICState *pApic = apicGetStateById(pDev, idCpu);
1485 apic_update_irq(pDev, pApic);
1495 static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *pApic)
1542 * @param pDev The device state.
1546 static void apicTimerSetInitialCount(APICDeviceInfo *pDev, APICState *pApic, uint32_t u32NewInitialCount)
1591 * @param pDev The device state.
1595 static void apicTimerSetLvt(APICDeviceInfo *pDev, APICState *pApic, uint32_t fNew)
1697 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1701 Assert(PDMCritSectIsOwner(pDev->pCritSectR3));
1706 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE,
1707 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDevIns, PDM_IRQ_LEVEL_HIGH));
1828 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1829 APICState *pApic = apicGetStateByCurEmt(pDev);
1837 STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
1858 int rc = apicReadRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, &u64Value, VINF_IOM_R3_MMIO_READ, false /*fMsr*/);
1865 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1866 APICState *pApic = apicGetStateByCurEmt(pDev);
1874 STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIOWrite));
1876 return apicWriteRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
1886 * @param pDev The PDM device instance.
1890 static uint64_t apicR3InfoReadReg(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg)
1893 int rc = apicReadRegister(pDev, pApic, iReg, &u64Value, VINF_SUCCESS, true /*fMsr*/);
1901 * @param pDev The PDM device instance.
1906 static void apicR3DumpVec(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp, uint32_t iStartReg)
1909 pHlp->pfnPrintf(pHlp, "%08x", apicR3InfoReadReg(pDev, pApic, iStartReg + i));
1916 * @param pDev The PDM device instance.
1921 static void apicR3DumpPending(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp, PCAPIC256BITREG pReg)
1944 * @param pDev The PDM device instance.
1948 static void apicR3InfoBasic(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
1953 u64 = apicR3InfoReadReg(pDev, pApic, 0x2);
1956 u64 = apicR3InfoReadReg(pDev, pApic, 0x3);
1960 u64 = apicR3InfoReadReg(pDev, pApic, 0x8);
1963 u64 = apicR3InfoReadReg(pDev, pApic, 0xA);
1966 u64 = apicR3InfoReadReg(pDev, pApic, 0xD);
1969 pHlp->pfnPrintf(pHlp, " DFR : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0xE));
1970 u64 = apicR3InfoReadReg(pDev, pApic, 0xF);
1976 apicR3DumpVec(pDev, pApic, pHlp, 0x10);
1977 apicR3DumpPending(pDev, pApic, pHlp, &pApic->isr);
1979 apicR3DumpVec(pDev, pApic, pHlp, 0x20);
1980 apicR3DumpPending(pDev, pApic, pHlp, &pApic->irr);
1987 * @param pDev The PDM device instance.
1991 static void apicR3InfoLVT(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
1999 u64 = apicR3InfoReadReg(pDev, pApic, 0x32);
2005 u64 = apicR3InfoReadReg(pDev, pApic, 0x35);
2014 u64 = apicR3InfoReadReg(pDev, pApic, 0x36);
2029 * @param pDev The PDM device instance.
2033 static void apicR3InfoTimer(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
2036 pHlp->pfnPrintf(pHlp, " Initial count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x38));
2037 pHlp->pfnPrintf(pHlp, " Current count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x39));
2038 uint64_t u64 = apicR3InfoReadReg(pDev, pApic, 0x3e);
2051 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2052 APICState *pApic = apicGetStateByCurEmt(pDev);
2055 apicR3InfoBasic(pDev, pApic, pHlp);
2057 apicR3InfoLVT(pDev, pApic, pHlp);
2059 apicR3InfoTimer(pDev, pApic, pHlp);
2070 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2072 SSMR3PutU32( pSSM, pDev->cCpus);
2073 SSMR3PutBool(pSSM, pDev->fIoApic);
2074 SSMR3PutU32( pSSM, pDev->enmVersion);
2086 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2092 APIC_FOREACH_BEGIN(pDev);
2104 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2116 if (cCpus != pDev->cCpus)
2117 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pDev->cCpus);
2121 if (fIoApic != pDev->fIoApic)
2122 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pDev->fIoApic);
2126 if (uApicVersion != (uint32_t)pDev->enmVersion)
2127 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pDev->enmVersion);
2134 APIC_LOCK(pDev, VERR_INTERNAL_ERROR_3);
2137 APIC_FOREACH_BEGIN(pDev);
2143 APIC_UNLOCK(pDev);
2152 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2153 TMTimerLock(pDev->paLapicsR3[0].pTimerR3, VERR_IGNORED);
2154 APIC_LOCK_VOID(pDev, VERR_IGNORED);
2157 for (VMCPUID i = 0; i < pDev->cCpus; i++)
2159 APICState *pApic = &pDev->CTX_SUFF(paLapics)[i];
2163 apicR3InitIpi(pDev, pApic);
2175 apicCpuClearInterrupt(pDev, pApic);
2179 pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmVersion);
2181 APIC_UNLOCK(pDev);
2182 TMTimerUnlock(pDev->paLapicsR3[0].pTimerR3);
2191 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2192 pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2193 pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2194 pDev->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pDev->paLapicsR3);
2195 pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2196 for (uint32_t i = 0; i < pDev->cCpus; i++)
2197 pDev->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pDev->paLapicsR3[i].pTimerR3);
2230 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2269 pDev->pDevInsR3 = pDevIns;
2270 pDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2271 pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2272 pDev->cCpus = cCpus;
2273 pDev->fIoApic = fIoApic;
2276 pDev->enmVersion = PDMAPICVERSION_APIC;
2287 rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->paLapicsR3);
2290 pDev->paLapicsR0 = MMHyperR3ToR0(pVM, pDev->paLapicsR3);
2291 pDev->paLapicsRC = MMHyperR3ToRC(pVM, pDev->paLapicsR3);
2294 apicR3StateInit(&pDev->paLapicsR3[i], i);
2365 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pDev->pApicHlpR3);
2367 pDev->pCritSectR3 = pDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2373 pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmVersion);
2379 uint32_t ApicBase = pDev->paLapicsR3[0].apicbase & ~0xfff;
2380 rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pDev,
2388 pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2389 pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2394 pDev->pApicHlpR0 = pDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2395 pDev->pCritSectR0 = pDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2406 APICState *pApic = &pDev->paLapicsR3[i];
2414 TMR3TimerSetCritSect(pApic->pTimerR3, pDev->pCritSectR3);
2420 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pDev),
2435 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2436 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2437 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2438 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2439 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2442 APICState *pApic = &pDev->paLapicsR3[i];