Cross Reference: /vbox/src/VBox/Devices/PC/DevACPI.cpp

Lines Matching defs:u32
1051 PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1053     Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1055         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1060     u32 >>= pThis->u8IndexShift;
1062     if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1065         u32 >>= 2;
1067     Assert(u32 < BAT_INDEX_LAST);
1068     pThis->uBatteryIndex = u32;
1132 PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1134     Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1136         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1141     if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1142         pThis->uSystemInfoIndex = u32;
1146         if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1148             if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1152         u32 >>= pThis->u8IndexShift;
1153         Assert(u32 < SYSTEM_INFO_INDEX_END);
1154         pThis->uSystemInfoIndex = u32;
1341 PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1345         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1348     Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));
1354             AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1359             AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1364             pThis->idCpuLockCheck = u32;
1368             if (u32 < pThis->cCpus)
1369                 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1371                 LogRel(("ACPI: CPU %u does not exist\n", u32));
1375             rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1405 PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1408         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1413     Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1414     u32 &= ~(RSR_EN | IGN_EN);
1415     u32 &= 0xffff;
1416     apicUpdatePm1a(pThis, pThis->pm1a_sts, u32);
1446 PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1449         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1454     Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1455     u32 &= 0xffff;
1456     if (u32 & PWRBTN_STS)
1458     u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1459     apicUpdatePm1a(pThis, u32, pThis->pm1a_en);
1489 PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1492         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1497     Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1498     u32 &= 0xffff;
1499     pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1537                 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1618 PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1621         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1626     Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1627     u32 = pThis->gpe0_sts & ~u32;
1628     apicR3UpdateGpe0(pThis, u32, pThis->gpe0_en);
1658 PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1661         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1666     Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1667     apicR3UpdateGpe0(pThis, pThis->gpe0_sts, u32);
1676 PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1678     Log(("acpiR3SmiWrite %#x\n", u32));
1680         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1685     if (u32 == ACPI_ENABLE)
1687     else if (u32 == ACPI_DISABLE)
1690         Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1699 PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1701     Log(("acpiR3ResetWrite: %#x\n", u32));
1704         return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1708     if (u32 == ACPI_RESET_REG_VAL)
1714         Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1724 PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1730             Log(("%#x\n", u32 & 0xff));
1733             Log(("%#6x\n", u32 & 0xffff));
1735             Log(("%#10x\n", u32));
1738             return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1746 PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1752             Log(("%c", u32 & 0xff));
1755             return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);