Cross Reference: /vbox/src/VBox/Devices/PC/BIOS/ahci.c

Lines Matching refs:iobase
104     uint16_t        iobase;
173 #define AHCI_WRITE_REG(iobase, reg, val)    \
174     outpd((iobase) + AHCI_REG_IDX, reg);    \
175     outpd((iobase) + AHCI_REG_DATA, val)
178 #define AHCI_READ_REG(iobase, reg, val)     \
179     outpd((iobase) + AHCI_REG_IDX, reg);    \
180     (val) = inpd((iobase) + AHCI_REG_DATA)
183 #define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val)     \
184     AHCI_WRITE_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
187 #define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val)      \
188     AHCI_READ_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
250 static void ahci_ctrl_set_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
252     outpd(iobase + AHCI_REG_IDX, reg);
253     outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) | mask);
259 static void ahci_ctrl_clear_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
261     outpd(iobase + AHCI_REG_IDX, reg);
262     outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
269 static uint8_t ahci_ctrl_is_bit_set(uint16_t iobase, uint16_t reg, uint32_t mask)
271     outpd(iobase + AHCI_REG_IDX, reg);
272     return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
301     io_base = ahci->iobase;
427     io_base = ahci->iobase;
474     ahci_ctrl_clear_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
477     while (ahci_ctrl_is_bit_set(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
494     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FB, ahci_addr_to_phys(&ahci->abFisRecv));
495     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FBU, 0);
498     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLB, ahci_addr_to_phys(&ahci->aCmdHdr));
499     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLBU, 0);
502     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IE, 0);
503     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IS, 0xffffffff);
505     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
650     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0x01);
655     VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0);
658     VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
664         VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
675         VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
685             ahci_ctrl_set_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
689             VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SIG, val);
875     ahci->iobase   = io_base;