Lines Matching defs:aCSR
167 #define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */
168 #define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */
169 #define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */
170 #define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */
171 #define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */
172 #define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */
173 #define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */
174 #define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */
175 #define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */
176 #define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */
177 #define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */
178 #define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */
179 #define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */
180 #define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */
182 #define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */
183 #define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */
185 #define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */
186 #define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */
187 #define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */
188 #define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */
189 #define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */
190 #define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */
199 #define CSR_IADR(S) (*(uint32_t*)((S)->aCSR + 1)) /**< Initialization Block Address */
200 #define CSR_CRBA(S) (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */
201 #define CSR_CXBA(S) (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */
202 #define CSR_NRBA(S) (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */
203 #define CSR_BADR(S) (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */
204 #define CSR_NRDA(S) (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */
205 #define CSR_CRDA(S) (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */
206 #define CSR_BADX(S) (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */
207 #define CSR_NXDA(S) (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */
208 #define CSR_CXDA(S) (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */
209 #define CSR_NNRD(S) (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */
210 #define CSR_NNXD(S) (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */
211 #define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */
212 #define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */
213 #define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */
214 #define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */
215 #define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */
216 #define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */
217 #define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */
218 #define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */
219 #define CSR_PXDA(S) (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/
220 #define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */
221 #define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */
222 #define CSR_NXBA(S) (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */
223 #define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */
224 #define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */
225 #define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */
226 #define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */
227 #define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */
228 #define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */
229 #define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */
328 uint16_t aCSR[CSR_MAX_REG];
1001 result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, pThis->aCSR + 12, 6);
1004 padr[0] = pThis->aCSR[12] & 0xff;
1005 padr[1] = pThis->aCSR[12] >> 8;
1006 padr[2] = pThis->aCSR[13] & 0xff;
1007 padr[3] = pThis->aCSR[13] >> 8;
1008 padr[4] = pThis->aCSR[14] & 0xff;
1009 padr[5] = pThis->aCSR[14] >> 8;
1037 if (RT_UNLIKELY(hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&pThis->aCSR[8])[0] != 0LL)
1042 return ((uint8_t*)(pThis->aCSR + 8))[index >> 3] & (1 << (index & 7));
1045 ladr[0] = pThis->aCSR[8] & 0xff;
1046 ladr[1] = pThis->aCSR[8] >> 8;
1047 ladr[2] = pThis->aCSR[9] & 0xff;
1048 ladr[3] = pThis->aCSR[9] >> 8;
1049 ladr[4] = pThis->aCSR[10] & 0xff;
1050 ladr[5] = pThis->aCSR[10] >> 8;
1051 ladr[6] = pThis->aCSR[11] & 0xff;
1052 ladr[7] = pThis->aCSR[11] >> 8;
1218 pThis->aCSR[0] = 0x0004;
1219 pThis->aCSR[3] = 0x0000;
1220 pThis->aCSR[4] = 0x0115;
1221 pThis->aCSR[5] = 0x0000;
1222 pThis->aCSR[6] = 0x0000;
1223 pThis->aCSR[8] = 0;
1224 pThis->aCSR[9] = 0;
1225 pThis->aCSR[10] = 0;
1226 pThis->aCSR[11] = 0;
1227 pThis->aCSR[12] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[0]);
1228 pThis->aCSR[13] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[1]);
1229 pThis->aCSR[14] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[2]);
1230 pThis->aCSR[15] &= 0x21c4;
1235 pThis->aCSR[80] = 0x1410;
1236 pThis->aCSR[88] = pThis->fAm79C973 ? CSR_VERSION_LOW_79C973 : CSR_VERSION_LOW_79C970A;
1237 pThis->aCSR[89] = CSR_VERSION_HIGH;
1238 pThis->aCSR[94] = 0x0000;
1239 pThis->aCSR[100] = 0x0200;
1240 pThis->aCSR[103] = 0x0105;
1241 pThis->aCSR[103] = 0x0105;
1243 pThis->aCSR[114] = 0x0000;
1244 pThis->aCSR[122] = 0x0000;
1245 pThis->aCSR[124] = 0x0000;
1257 register uint16_t csr0 = pThis->aCSR[0];
1267 if ( ( (csr0 & ~pThis->aCSR[3]) & 0x5f00)
1268 || (((pThis->aCSR[4]>>1) & ~pThis->aCSR[4]) & 0x0115)
1269 || (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0048))
1271 if ( ( !(pThis->aCSR[3] & 0x4000) && !!(csr0 & 0x4000)) /* BABL */
1272 ||( !(pThis->aCSR[3] & 0x1000) && !!(csr0 & 0x1000)) /* MISS */
1273 ||( !(pThis->aCSR[3] & 0x0100) && !!(csr0 & 0x0100)) /* IDON */
1274 ||( !(pThis->aCSR[3] & 0x0200) && !!(csr0 & 0x0200)) /* TINT */
1275 ||( !(pThis->aCSR[3] & 0x0400) && !!(csr0 & 0x0400)) /* RINT */
1276 ||( !(pThis->aCSR[3] & 0x0800) && !!(csr0 & 0x0800)) /* MERR */
1277 ||( !(pThis->aCSR[4] & 0x0001) && !!(pThis->aCSR[4] & 0x0002)) /* JAB */
1278 ||( !(pThis->aCSR[4] & 0x0004) && !!(pThis->aCSR[4] & 0x0008)) /* TXSTRT */
1279 ||( !(pThis->aCSR[4] & 0x0010) && !!(pThis->aCSR[4] & 0x0020)) /* RCVO */
1280 ||( !(pThis->aCSR[4] & 0x0100) && !!(pThis->aCSR[4] & 0x0200)) /* MFCO */
1281 ||(!!(pThis->aCSR[5] & 0x0040) && !!(pThis->aCSR[5] & 0x0080)) /* EXDINT */
1282 ||(!!(pThis->aCSR[5] & 0x0008) && !!(pThis->aCSR[5] & 0x0010)) /* MPINT */)
1290 if (pThis->aCSR[4] & 0x0080) /* UINTCMD */
1292 pThis->aCSR[4] &= ~0x0080; /* clear UINTCMD */
1293 pThis->aCSR[4] |= 0x0040; /* set UINT */
1296 if (pThis->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */)
1302 if (!!(pThis->aCSR[4] & 0x0080) && CSR_INEA(pThis)) /* UINTCMD */
1304 pThis->aCSR[4] &= ~0x0080;
1305 pThis->aCSR[4] |= 0x0040; /* set UINT */
1313 if (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0500)
1315 if ( (!!(pThis->aCSR[5] & 0x0400) && !!(pThis->aCSR[5] & 0x0800)) /* SINT */
1316 ||(!!(pThis->aCSR[5] & 0x0100) && !!(pThis->aCSR[5] & 0x0200)) /* SLPINT */)
1323 if ((pThis->aCSR[7] & 0x0C00) == 0x0C00) /* STINT + STINTE */
1326 pThis->aCSR[0] = csr0;
1440 pThis->aCSR[15] = RT_LE2H_U16(initblk.mode); \
1443 pThis->aCSR[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \
1444 pThis->aCSR[ 8] = RT_LE2H_U16(initblk.ladrf1); \
1445 pThis->aCSR[ 9] = RT_LE2H_U16(initblk.ladrf2); \
1446 pThis->aCSR[10] = RT_LE2H_U16(initblk.ladrf3); \
1447 pThis->aCSR[11] = RT_LE2H_U16(initblk.ladrf4); \
1448 pThis->aCSR[12] = RT_LE2H_U16(initblk.padr1); \
1449 pThis->aCSR[13] = RT_LE2H_U16(initblk.padr2); \
1450 pThis->aCSR[14] = RT_LE2H_U16(initblk.padr3); \
1466 pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
1525 pThis->aCSR[0] |= 0x0101; /* Initialization done */
1526 pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1537 pThis->aCSR[0] |= 0x0010; /* set TXON */
1539 pThis->aCSR[0] |= 0x0020; /* set RXON */
1540 pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1541 pThis->aCSR[0] |= 0x0002; /* STRT */
1551 pThis->aCSR[0] = 0x0004;
1552 pThis->aCSR[4] &= ~0x02c2;
1553 pThis->aCSR[5] &= ~0x0011;
1837 pThis->aCSR[0] |= 0x1000; /* Set MISS flag */
1982 pThis->aCSR[0] |= 0x0400;
2271 pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */
2284 pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */
2298 pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2312 pThis->aCSR[0] &= ~0x0008;
2350 pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2496 pThis->aCSR[0] |= 0x0200; /* set TINT */
2500 pThis->aCSR[0] &= ~0x0010; /* clear TXON */
2567 pThis->aCSR[0] &= ~0x0008; /* clear TDMD */
2569 pThis->aCSR[4] |= 0x0008; /* set TXSTRT */
2591 pThis->aCSR[0] |= 0x0200; /* set TINT */
2757 uint16_t csr0 = pThis->aCSR[0];
2768 Log(("#%d CSR0: old=%#06x new=%#06x\n", PCNET_INST_NR, pThis->aCSR[0], csr0));
2777 pThis->aCSR[0] = csr0;
2838 pThis->aCSR[4] &= ~(val & 0x026a);
2840 val |= pThis->aCSR[4] & 0x026a;
2843 pThis->aCSR[5] &= ~(val & 0x0a90);
2845 val |= pThis->aCSR[5] & 0x0a90;
2849 uint16_t csr7 = pThis->aCSR[7];
2853 pThis->aCSR[7] = csr7;
2857 if ((pThis->aCSR[15] & 0x8000) != (uint16_t)(val & 0x8000) && pThis->pDrvR3)
2934 pThis->aCSR[u32RAP - 4] = val;
2940 pThis->aCSR[u32RAP] = val;
2966 val = pThis->aCSR[0];
2979 val = pThis->aCSR[89];
2981 val |= pThis->aCSR[88];
2984 val = pThis->aCSR[u32RAP];
3013 pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
3028 pThis->aCSR[58] = val;
3248 pThis->aCSR[58 ] = /* CSR58 is an alias for BCR20 */
3797 pThis->aCSR[7] |= 0x0800; /* STINT */
3828 pThis->aCSR[0] &= ~(RT_BIT(15) | RT_BIT(13)); /* ERR | CERR - probably not 100% correct either... */
3949 pThis->aCSR[0]);
3953 pThis->aCSR[1]);
3957 pThis->aCSR[2]);
3961 pThis->aCSR[3],
3962 !!(pThis->aCSR[3] & RT_BIT(2)), !!(pThis->aCSR[3] & RT_BIT(3)), !!(pThis->aCSR[3] & RT_BIT(4)), CSR_LAPPEN(pThis),
3963 CSR_DXSUFLO(pThis), !!(pThis->aCSR[3] & RT_BIT(8)), !!(pThis->aCSR[3] & RT_BIT(9)), !!(pThis->aCSR[3] & RT_BIT(10)),
3964 !!(pThis->aCSR[3] & RT_BIT(11)), !!(pThis->aCSR[3] & RT_BIT(12)), !!(pThis->aCSR[3] & RT_BIT(14)));
3969 pThis->aCSR[4],
3970 !!(pThis->aCSR[4] & RT_BIT( 0)), !!(pThis->aCSR[4] & RT_BIT( 1)), !!(pThis->aCSR[4] & RT_BIT( 2)), !!(pThis->aCSR[4] & RT_BIT( 3)),
3971 !!(pThis->aCSR[4] & RT_BIT( 4)), !!(pThis->aCSR[4] & RT_BIT( 5)), !!(pThis->aCSR[4] & RT_BIT( 6)), !!(pThis->aCSR[4] & RT_BIT( 7)),
3972 !!(pThis->aCSR[4] & RT_BIT( 8)), !!(pThis->aCSR[4] & RT_BIT( 9)), !!(pThis->aCSR[4] & RT_BIT(10)), !!(pThis->aCSR[4] & RT_BIT(11)),
3973 !!(pThis->aCSR[4] & RT_BIT(12)), !!(pThis->aCSR[4] & RT_BIT(13)), !!(pThis->aCSR[4] & RT_BIT(14)), !!(pThis->aCSR[4] & RT_BIT(15)));
3977 pThis->aCSR[5]);
3981 pThis->aCSR[6],
3982 (pThis->aCSR[6] >> 8) & 0xf, (pThis->aCSR[6] >> 12) & 0xf);
3986 pThis->aCSR[8], pThis->aCSR[9], pThis->aCSR[10], pThis->aCSR[11],
3987 (uint64_t)(pThis->aCSR[ 8] & 0xffff)
3988 | (uint64_t)(pThis->aCSR[ 9] & 0xffff) << 16
3989 | (uint64_t)(pThis->aCSR[10] & 0xffff) << 32
3990 | (uint64_t)(pThis->aCSR[11] & 0xffff) << 48);
3994 pThis->aCSR[12], pThis->aCSR[13], pThis->aCSR[14],
3995 pThis->aCSR[12] & 0xff,
3996 (pThis->aCSR[12] >> 8) & 0xff,
3997 pThis->aCSR[13] & 0xff,
3998 (pThis->aCSR[13] >> 8) & 0xff,
3999 pThis->aCSR[14] & 0xff,
4000 (pThis->aCSR[14] >> 8) & 0xff);
4005 pThis->aCSR[15],
4006 !!(pThis->aCSR[15] & RT_BIT( 0)), !!(pThis->aCSR[15] & RT_BIT( 1)), !!(pThis->aCSR[15] & RT_BIT( 2)), !!(pThis->aCSR[15] & RT_BIT( 3)),
4007 !!(pThis->aCSR[15] & RT_BIT( 4)), !!(pThis->aCSR[15] & RT_BIT( 5)), !!(pThis->aCSR[15] & RT_BIT( 6)), (pThis->aCSR[15] >> 7) & 3,
4008 !!(pThis->aCSR[15] & RT_BIT( 9)), !!(pThis->aCSR[15] & RT_BIT(10)), !!(pThis->aCSR[15] & RT_BIT(11)),
4009 !!(pThis->aCSR[15] & RT_BIT(12)), !!(pThis->aCSR[15] & RT_BIT(13)), !!(pThis->aCSR[15] & RT_BIT(14)), !!(pThis->aCSR[15] & RT_BIT(15)));
4013 pThis->aCSR[46], pThis->aCSR[46] & 0xffff);
4017 pThis->aCSR[47], pThis->aCSR[47] & 0xffff);
4021 pThis->aCSR[58],
4022 pThis->aCSR[58] & 0x7f,
4023 (pThis->aCSR[58] & 0x7f) == 0 ? "C-LANCE / PCnet-ISA"
4024 : (pThis->aCSR[58] & 0x7f) == 1 ? "ILACC"
4025 : (pThis->aCSR[58] & 0x7f) == 2 ? "PCNet-PCI II"
4026 : (pThis->aCSR[58] & 0x7f) == 3 ? "PCNet-PCI II controller"
4028 !!(pThis->aCSR[58] & RT_BIT(8)), !!(pThis->aCSR[58] & RT_BIT(9)), !!(pThis->aCSR[58] & RT_BIT(10)));
4032 pThis->aCSR[112], pThis->aCSR[112] & 0xffff);
4036 pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(0)));
4040 pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(3)));
4160 pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR (this is probably wrong) */
4227 SSMR3PutMem(pSSM, pThis->aCSR, sizeof(pThis->aCSR));
4314 SSMR3GetMem(pSSM, &pThis->aCSR, sizeof(pThis->aCSR));
4360 : (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
4422 pThis->aCSR[0] |= 0x1000; /* Set MISS flag */
4600 pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR (this is probably wrong) */
4609 pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR (this is probably wrong) */