Cross Reference: /vbox/src/VBox/Devices/Network/DevE1000.cpp

Lines Matching refs:pPciDev
6058 static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
6060     PE1KSTATE pThis = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
6067             rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
6070                 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
6073                 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
6086             rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
6090                 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
6093                 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
7347 static DECLCALLBACK(void) e1kConfigurePciDev(PPCIDEVICE pPciDev, E1KCHIP eChip)
7351     PCIDevSetVendorId(pPciDev, g_Chips[eChip].uPCIVendorId);
7352     PCIDevSetDeviceId(pPciDev, g_Chips[eChip].uPCIDeviceId);
7353     PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
7354     PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
7356     PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND,            0x0000);
7358     PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
7361     PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID,          0x02);
7363     PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG,           0x00);
7364     PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE,       0x0200);
7366     PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE,          0x00);
7368     PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7370     PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7372     PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7374     PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS,    0x00000000);
7376     PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST,      0xDC);
7378     PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN,        0x01);
7380     PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT,              0xFF);
7381     PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT,              0x00);
7385     PCIDevSetByte( pPciDev, 0xDC,            VBOX_PCI_CAP_ID_PM);
7387     PCIDevSetByte( pPciDev, 0xDC + 1,                      0xE4);
7389     PCIDevSetWord( pPciDev, 0xDC + 2,
7392     PCIDevSetWord( pPciDev, 0xDC + 4,                    0x0000);
7394     PCIDevSetByte( pPciDev, 0xDC + 6,                      0x00);
7396     PCIDevSetByte( pPciDev, 0xDC + 7,                      0x00);
7400     PCIDevSetByte( pPciDev, 0xE4,          VBOX_PCI_CAP_ID_PCIX);
7402     PCIDevSetByte( pPciDev, 0xE4 + 1,                      0x80);
7405     PCIDevSetByte( pPciDev, 0xE4 + 1,                      0x00);
7408     PCIDevSetWord( pPciDev, 0xE4 + 2,        VBOX_PCI_X_CMD_ERO);
7411     PCIDevSetDWord(pPciDev, 0xE4 + 4,                0x0040FFF8);