Lines Matching defs:pSVGAState
222 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),
800 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
801 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
804 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
805 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
808 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
809 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
815 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
816 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
820 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
823 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
831 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
836 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
838 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1049 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1302 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1303 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1327 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1328 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1331 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1332 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1333 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1339 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1340 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1342 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1345 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1346 pSVGAState->aGMR[idGMR].paDesc = NULL;
1896 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1901 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1903 PGMR pGMR = &pSVGAState->aGMR[i];
1932 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1933 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1954 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1955 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1968 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
1970 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1972 PGMR pGMR = &pSVGAState->aGMR[i];
1997 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2000 static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGASTATE pSVGAState, uint32_t offFifoMin)
2007 if (pSVGAState->cBusyDelayedEmts > 0)
2011 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2016 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2020 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2044 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2050 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGASTATE pSVGAState)
2077 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2098 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2112 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2123 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2128 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2151 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2183 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
2221 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2226 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2289 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2310 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2312 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2317 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2334 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2484 if (pSVGAState->Cursor.fActive)
2485 RTMemFree(pSVGAState->Cursor.pData);
2487 pSVGAState->Cursor.fActive = true;
2488 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2489 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2490 pSVGAState->Cursor.width = pCursor->width;
2491 pSVGAState->Cursor.height = pCursor->height;
2492 pSVGAState->Cursor.cbData = cbCursorShape;
2493 pSVGAState->Cursor.pData = pCursorCopy;
2559 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2597 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2745 pSVGAState->GMRFB.ptr = pCmd->ptr;
2746 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2747 pSVGAState->GMRFB.format = pCmd->format;
2760 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2785 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
2791 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
2814 pSVGAState->colorAnnotation = pCmd->color;
2910 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
2912 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3058 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3060 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3118 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3120 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3175 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3183 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3198 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3220 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3240 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3243 if (pSVGAState->aGMR[idGMR].numDescriptors)
3245 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3257 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3277 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3335 pGMR = &pSVGAState->aGMR[src.gmrId];
3562 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3574 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3578 if (pSVGAState->Cursor.fActive)
3580 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3581 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3583 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3588 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3590 PGMR pGMR = &pSVGAState->aGMR[i];
3643 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3649 if (pSVGAState->Cursor.fActive)
3656 pSVGAState->Cursor.xHotspot,
3657 pSVGAState->Cursor.yHotspot,
3658 pSVGAState->Cursor.width,
3659 pSVGAState->Cursor.height,
3660 pSVGAState->Cursor.pData);
3672 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3684 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3688 if (pSVGAState->Cursor.fActive)
3690 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3695 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3697 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
3700 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
3702 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3736 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3739 if (!pSVGAState)
3755 memset(pThis->svga.pSVGAState, 0, sizeof(VMSVGASTATE));
3792 PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3808 if (pSVGAState)
3811 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
3813 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
3814 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
3817 if (pSVGAState->Cursor.fActive)
3818 RTMemFree(pSVGAState->Cursor.pData);
3820 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3822 if (pSVGAState->aGMR[i].paDesc)
3823 RTMemFree(pSVGAState->aGMR[i].paDesc);
3825 RTMemFree(pSVGAState);
3852 PVMSVGASTATE pSVGAState;
3859 pThis->svga.pSVGAState = RTMemAllocZ(sizeof(VMSVGASTATE));
3860 AssertReturn(pThis->svga.pSVGAState, VERR_NO_MEMORY);
3861 pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3887 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
3945 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
3946 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
3947 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
3948 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
3949 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
3950 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
3951 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
3952 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
3953 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
3954 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");