45    operation is performed at the PCI memory address specified by Address for the width specified
52    @param[in]   Address   The base address of the memory operations. The caller is
53                           responsible for aligning Address if required.
74   IN  UINT64                                 Address,
86    performed at the PCI I/O address specified by Address for the width specified by Width.
93    @param[in] Address   The base address of the I/O operations. The caller is responsible
94                         for aligning Address if required.
115   IN  UINT64                                 Address,
132    @param[in]   Address   The base address of the memory operation. The caller is
133                           responsible for aligning the Address if required.
135                           Width size * Count, starting at Address.
150   IN     UINT64                                 Address,
165    @param[in]   Address   The base address of the memory operation. The caller is
166                           responsible for aligning the Address if required.
168                           Width size * Count, starting at Address.
182   IN     UINT64                                 Address,
193                             aligning the Address if required.
195                             size * Count, starting at Address.
221                             aligning the Address if required.
223                             size * Count, starting at Address.
288    @param[in]   Address   The address within the PCI configuration space for the PCI controller.
290                           moved is Width size * Count, starting at Address.
305   IN     UINT64                                 Address,
321    @param[in]   Address   The address within the PCI configuration space for the PCI controller.
323                           moved is Width size * Count, starting at Address.
338   IN     UINT64                                 Address,
554    describe the current resources allocated to a PCI root bridge. These are the QWORD Address
556    QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
558    Address Space Descriptors followed by an End Tag.
736   @param[in] Address        The base address of the I/O operation. 
738                             bytes moved is Width size * Count, starting at Address.
746   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
755   IN UINT64                                 Address,
798   // Check to see if Address is aligned
800   if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
809   // Address + Size * Count.  If the following condition is met, then the transfer
812   //    Address + Size * Count > Limit + 1
828     PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
838       Address = PciRbAddr->ExtendedRegister;
840       Address = PciRbAddr->Register;
846   if (Address < Base) {
851     if (Address > Limit) {
859     if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
875                               moved is Width size * Count, starting at Address.
890   IN     UINT64                                 Address,
901   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
909   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
913           MmioWrite8 ((UINTN)Address, *Uint8Buffer);
916           MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
919           MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
922           MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
935           *Uint8Buffer = MmioRead8 ((UINTN)Address);
938           *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
941           *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
944           *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
967                               moved is Width size * Count, starting at Address.
982   IN     UINT64                                 Address,
993   Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
1009           ASMOutStrU8((RTIOPORT)Address, (const uint8_t*)Buffer, (size_t)Count);
1011           ASMInStrU8((RTIOPORT)Address, (uint8_t*)Buffer, (size_t)Count);
1015           ASMOutStrU16((RTIOPORT)Address, (const uint16_t*)Buffer, (size_t)Count);
1017           ASMInStrU16((RTIOPORT)Address, (uint16_t*)Buffer, (size_t)Count);
1021           ASMOutStrU32((RTIOPORT)Address, (const uint32_t*)Buffer, (size_t)Count);
1023           ASMInStrU32((RTIOPORT)Address, (uint32_t*)Buffer, (size_t)Count);
1030   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
1034           IoWrite8 ((UINTN)Address, *Uint8Buffer);
1037           IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
1040           IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
1053           *Uint8Buffer = IoRead8 ((UINTN)Address);
1056           *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
1059           *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
1085                               moved is Width size * Count, starting at Address.
1100   IN UINT64                                 Address,
1113   Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
1118   PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
1182    operation is performed at the PCI memory address specified by Address for the width specified
1189    @param[in]   Address   The base address of the memory operations. The caller is
1190                           responsible for aligning Address if required.
1211   IN  UINT64                                 Address,
1233   Status = This->Mem.Read (This, Width, Address, 1, Result);
1265       Status = This->Mem.Read (This, Width, Address, 1, Result);
1285    performed at the PCI I/O address specified by Address for the width specified by Width.
1292    @param[in] Address   The base address of the I/O operations. The caller is responsible
1293                         for aligning Address if required.
1314   IN  UINT64                                 Address,
1337   Status = This->Io.Read (This, Width, Address, 1, Result);
1366       Status = This->Io.Read (This, Width, Address, 1, Result);
1391    @param[in]   Address   The base address of the memory operation. The caller is
1392                           responsible for aligning the Address if required.
1394                           Width size * Count, starting at Address.
1409   IN     UINT64                                 Address,
1414   return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
1427    @param[in]   Address   The base address of the memory operation. The caller is
1428                           responsible for aligning the Address if required.
1430                           Width size * Count, starting at Address.
1444   IN     UINT64                                 Address,
1449   return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);  
1457    @param[in]   Address     The base address of the I/O operation. The caller is responsible for
1458                             aligning the Address if required.
1460                             size * Count, starting at Address.
1475   IN     UINT64                                 Address,
1480   return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);  
1488    @param[in]   Address     The base address of the I/O operation. The caller is responsible for
1489                             aligning the Address if required.
1491                             size * Count, starting at Address.
1506   IN       UINT64                                  Address,
1511   return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);  
1614    @param[in]   Address   The address within the PCI configuration space for the PCI controller.
1616                           moved is Width size * Count, starting at Address.
1631   IN       UINT64                                 Address,
1636   return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
1650    @param[in]   Address   The address within the PCI configuration space for the PCI controller.
1652                           moved is Width size * Count, starting at Address.
1667   IN       UINT64                                 Address,
1672   return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
2120    describe the current resources allocated to a PCI root bridge. These are the QWORD Address
2122    QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
2124    Address Space Descriptors followed by an End Tag.

Indexes created Tue Jul 24 14:28:13 CEST 2018