Lines Matching refs:DRQ
2206 // Before write to all the following registers, BSY DRQ must be 0.
2263 // Before data transfer, BSY should be 0 and DRQ should be 1.
2365 // before each data transfer stream, the host should poll DRQ bit ready,
2410 // After data transfer is completed, normally, DRQ bit should clear.
2576 Check whether DRQ is clear in the Status Register. (BSY must also be cleared)
2578 DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is
2610 // wait for BSY == 0 and DRQ == 0
2612 if ((StatusRegister & (DRQ | BSY)) == 0) {
2660 Check whether DRQ is clear in the Alternate Status Register.
2662 wait infinitely for DRQ clear. Otherwise, it will return EFI_TIMEOUT when specified time is
2694 // wait for BSY == 0 and DRQ == 0
2696 if ((AltStatusRegister & (DRQ | BSY)) == 0) {
2742 Check whether DRQ is ready in the Status Register. (BSY must also be cleared)
2744 DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is
2778 // BSY==0,DRQ==1
2780 if ((StatusRegister & (BSY | DRQ)) == DRQ) {
2826 Check whether DRQ is ready in the Alternate Status Register.
2829 DRQ ready. Otherwise, it will return EFI_TIMEOUT when specified time is
2862 // BSY==0,DRQ==1
2864 if ((AltStatusRegister & (BSY | DRQ)) == DRQ) {