Lines Matching refs:UINT32
26 UINT32
30 IN UINT32 Offset
33 UINT32 Data;
63 IN UINT32 Offset,
64 IN UINT32 Data
93 IN UINT32 Offset,
94 IN UINT32 AndData
97 UINT32 Data;
120 IN UINT32 Offset,
121 IN UINT32 OrData
124 UINT32 Data;
153 IN UINT32 MaskValue,
154 IN UINT32 TestValue,
158 UINT32 Value;
159 UINT32 Delay;
161 Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
167 Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
201 IN UINT32 MaskValue,
202 IN UINT32 TestValue,
206 UINT32 Value;
207 UINT32 Delay;
209 Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
220 Value = *(volatile UINT32 *) (UINTN) Address;
256 IN UINT32 MaskValue,
257 IN UINT32 TestValue,
261 UINT32 Value;
267 Value = *(volatile UINT32 *) Address;
303 UINT32 Data;
304 UINT32 Offset;
333 UINT32 Offset;
370 UINT32 Offset;
371 UINT32 Data;
409 UINT32 Offset;
444 UINT32 Offset;
445 UINT32 Data;
464 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
506 IN UINT32 DataLength
510 UINT32 PrdtNumber;
511 UINT32 PrdtIndex;
515 UINT32 Offset;
555 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
564 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
675 IN UINT32 DataCount,
687 UINT32 Delay;
690 UINT32 PortTfd;
691 UINT32 PrdCount;
760 Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
763 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
773 PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
810 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
877 IN UINT32 DataCount,
891 UINT32 PortTfd;
924 Task->RetryTimes = (UINT32) (DivU64x32(Timeout, 1000) + 1);
1016 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1098 UINT32 PortTfd;
1152 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1195 UINT32 Offset;
1196 UINT32 Data;
1206 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1240 UINT32 CmdSlotBit;
1242 UINT32 PortStatus;
1243 UINT32 StartCmd;
1244 UINT32 PortTfd;
1245 UINT32 Offset;
1246 UINT32 Capability;
1253 CmdSlotBit = (UINT32) (1 << CommandSlot);
1336 UINT32 Offset;
1355 AhciAndReg (PciIo, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);
1402 UINT32 Delay;
1403 UINT32 Value;
1409 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
1461 UINT32 Value;
1492 Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1761 IN UINT32 FeatureSpecificData
1822 UINT32 Length;
1906 UINT32 Capability;
2144 UINT32 Capability;
2146 UINT32 PortImplementBitMap;
2152 UINT32 Offset;
2153 UINT32 Data;
2158 UINT32 PhyDetectDelay;
2407 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));