Lines Matching refs:UINT8
39 UINT8 RevisionID;
40 UINT8 ClassCode[3];
41 UINT8 CacheLineSize;
42 UINT8 LatencyTimer;
43 UINT8 HeaderType;
44 UINT8 BIST;
53 UINT8 CapabilityPtr;
54 UINT8 Reserved1[3];
56 UINT8 InterruptLine;
57 UINT8 InterruptPin;
58 UINT8 MinGnt;
59 UINT8 MaxLat;
69 UINT8 PrimaryBus;
70 UINT8 SecondaryBus;
71 UINT8 SubordinateBus;
72 UINT8 SecondaryLatencyTimer;
73 UINT8 IoBase;
74 UINT8 IoLimit;
84 UINT8 CapabilityPtr;
85 UINT8 Reserved[3];
87 UINT8 InterruptLine;
88 UINT8 InterruptPin;
108 UINT8 PciBusNumber; // PCI Bus Number
109 UINT8 CardBusBusNumber; // CardBus Bus Number
110 UINT8 SubordinateBusNumber; // Subordinate Bus Number
111 UINT8 CardBusLatencyTimer; // CardBus Latency Timer
120 UINT8 InterruptLine; // Interrupt Line
121 UINT8 InterruptPin; // Interrupt Pin
389 UINT8 Reserved[0x16];
395 UINT8 Size512;
396 UINT8 InitEntryPoint[3];
397 UINT8 Reserved[0x12];
407 UINT8 Revision;
408 UINT8 ClassCode[3];
411 UINT8 CodeType;
412 UINT8 Indicator;
428 UINT8 CapabilityID;
429 UINT8 NextItemPtr;
439 UINT8 BridgeExtention;
440 UINT8 Data;
448 UINT8 Rev;
449 UINT8 Reserved;
468 UINT8 ExpnsSlotReg;
469 UINT8 ChassisNo;