Lines Matching refs:fWritable
1232 uint8_t fWritable;
1252 { 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1253 { 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1254 { 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1255 { 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1257 { 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1258 { 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1259 { 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1261 { 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1262 { 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1264 { 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1265 { 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1266 { 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1267 { 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1268 { 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1269 { 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1270 { 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1271 { 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1272 { 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1273 { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1274 { 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1276 { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1280 { 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1353 if (!s_aFields[i].fWritable)
2087 bool fWritable = false;
2108 fWritable = false;
2112 fWritable = true;
2130 fWritable = false;
2133 fWritable = true;
2139 fWritable = false;
2189 if (fWritable)