Lines Matching defs:pBus
176 static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
215 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
223 uDevFnBridge = pBus->aPciDev.devfn;
227 pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
228 pPciDevBus = &pBus->aPciDev;
229 } while (pBus->iBus != 0);
231 AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
232 ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
564 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
568 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
573 PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
585 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
598 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
603 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
632 PICH9PCIBUS pBus = &pGlobals->aPciBus;
650 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
652 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
765 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
768 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
774 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
779 Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
820 PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
835 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
941 PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
948 || iDev >= (int)RT_ELEMENTS(pBus->apDevices)
958 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
971 rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
982 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
989 || iDev >= (int)RT_ELEMENTS(pBus->apDevices))
998 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1070 static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1075 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1077 PPCIDEVICE pDev = pBus->apDevices[i];
1153 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1158 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1160 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1170 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1181 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1187 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1189 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1201 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1386 * @param pBus The bus which data is being loaded.
1391 static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1409 for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1411 PPCIDEVICE pDev = pBus->apDevices[i];
1438 AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1443 pDev = pBus->apDevices[i];
1487 pDev = pBus->apDevices[i];
1533 PICH9PCIBUS pBus = &pThis->aPciBus;
1561 return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1838 PICH9PCIBUS pBus = &pGlobals->aPciBus;
1841 PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1852 pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1858 while (pBus->iBus != 0)
1861 iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1862 pBus = pBus->aPciDev.Int.s.pBusR3;
1878 * @param pBus The PCI bus to initialize.
1882 static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1885 PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1894 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1896 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1905 pBus,
1929 PICH9PCIBUS pBus = &pGlobals->aPciBus;
1930 ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1964 return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1972 return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2062 MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2063 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2073 MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2074 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2201 static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
2209 if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2215 for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2217 if ( !pBus->apDevices[iPos]
2218 && !pBus->apDevices[iPos + 1]
2219 && !pBus->apDevices[iPos + 2]
2220 && !pBus->apDevices[iPos + 3]
2221 && !pBus->apDevices[iPos + 4]
2222 && !pBus->apDevices[iPos + 5]
2223 && !pBus->apDevices[iPos + 6]
2224 && !pBus->apDevices[iPos + 7])
2236 static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2238 PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2252 static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2262 if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2279 pBus->apDevices[iDev] &&
2280 pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2283 pszName, pBus->apDevices[iDev]->name, iDev));
2287 if (pBus->apDevices[iDev])
2290 bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2303 if (!pBus->apDevices[iDev + i])
2305 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2306 pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2307 pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2308 pBus->apDevices[iDev + i] = NULL;
2317 pPciDev->Int.s.pBusR3 = pBus;
2318 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2319 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2322 pBus->apDevices[iDev] = pPciDev;
2325 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2328 Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2329 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2330 pBus->cBridges++;
2334 iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 | (iDev << 8), pszName));
2347 static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2349 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2351 PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2361 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2449 if (pBus->cBridges > 0)
2452 pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2453 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2455 PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2470 PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2474 ich9pciBusInfo(pBus, pHlp, 0, false);
2478 ich9pciBusInfo(pBus, pHlp, 0, true);
2532 PICH9PCIBUS pBus = &pGlobals->aPciBus;
2570 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2574 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2577 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2579 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2580 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2592 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2593 PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2594 PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2595 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2596 PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2597 PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2598 PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2599 PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2601 pBus->aPciDev.pDevIns = pDevIns;
2603 ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2658 sizeof(*pBus) + 16*128, "pgm",
2731 PICH9PCIBUS pBus = &pGlobals->aPciBus;
2734 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2736 if (pBus->apDevices[i])
2737 ich9pciResetDevice(pBus->apDevices[i]);
2740 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2742 if (pBus->papBridgesR3[iBridge])
2743 ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2765 PICH9PCIBUS pBus = &pGlobals->aPciBus;
2768 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2769 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2772 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2773 ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2810 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2811 pBus->pDevInsR3 = pDevIns;
2812 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2813 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2814 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));
2826 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2830 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2833 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2835 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2836 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2845 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2846 PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2847 PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2848 PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2849 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2850 PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2851 PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2852 PCIDevSetCommand( &pBus->aPciDev, 0x00);
2853 PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2854 PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2860 PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2862 pBus->aPciDev.pDevIns = pDevIns;
2865 pciDevSetPci2PciBridge(&pBus->aPciDev);
2866 pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2867 pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2872 rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2884 pBus->iBus = iInstance + 1;
2891 sizeof(*pBus) + 16*128,
2908 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2911 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2912 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2913 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2916 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2918 if (pBus->apDevices[i])
2919 ich9pciResetDevice(pBus->apDevices[i]);
2929 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2930 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2933 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2934 ich9pciRelocateDevice(pBus->apDevices[i], offDelta);