Lines Matching refs:uDevFn
586 static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
589 slot_addend = (uDevFn >> 3) - 1;
593 static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
595 return (irq_num + (uDevFn >> 3)) & 7;
603 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
611 int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
648 * @param uDevFn The device number on the host bus which will raise the IRQ
653 * @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
654 * In that case uDevFn will be the slot of the bridge which is needed to calculate the
657 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
685 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
687 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
701 irq_num = pci_slot_get_pirq(uDevFn, iIrq);
741 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
820 static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
823 (uDevFn << 8) | addr;
827 static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
830 (uDevFn << 8) | (addr & ~3);
834 static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
837 (uDevFn << 8) | (addr & ~3);
841 static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
844 (uDevFn << 8) | addr;
851 static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
854 (uDevFn << 8) | (addr & ~3);
861 static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
864 (uDevFn << 8) | (addr & ~3);
874 static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
885 uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
888 cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
897 pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
900 pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
903 static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
909 devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
910 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
911 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
923 pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
924 pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
930 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
931 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
932 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
933 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
940 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
946 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
947 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
952 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
953 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
960 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
969 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
975 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
979 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
980 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
983 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
993 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
999 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1010 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1023 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1031 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1038 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1039 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1040 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1041 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1059 u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1060 pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1061 u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1077 Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1087 pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1097 pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1100 uint8_t uBridgeDevFn = uDevFn;
1112 pin = pci_slot_get_pirq(uDevFn, pin);
1114 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);