Cross Reference: /vbox/src/VBox/Devices/Bus/DevPCI.cpp

Lines Matching refs:uBus
140     uint8_t             uBus;
820 static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
822     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
827 static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
829     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
834 static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
836     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
841 static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
843     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
851 static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
853     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
861 static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
863     pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
874 static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
885     uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
888     cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
897     pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
900     pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
903 static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
909     devclass  = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
910     vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
911     device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
923                     pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
924                     pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
930                     pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
931                     pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
932                     pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
933                     pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
940                 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
946                 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
947                                   pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
952                 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
953                 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
960                         pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
969                     pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
975                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
977                 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
978                 pGlobals->uBus++;
979                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
980                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
993                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
999                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1007                     pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1010                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1023                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1031                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1038                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1039                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1040                 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1041                 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1059                     u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1060                     pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1061                     u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1077                     Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1087                         pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1097         pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1114             pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1851     pGlobals->uBus = 0;