Lines Matching refs:fWritable
1288 uint8_t fWritable;
1308 { 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1309 { 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1310 { 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1311 { 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1313 { 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1314 { 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1315 { 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1317 { 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1318 { 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1320 { 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1321 { 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1322 { 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1323 { 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1324 { 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1325 { 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1326 { 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1327 { 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1328 { 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1329 { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1330 { 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1332 { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1336 { 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1407 if (!s_aFields[i].fWritable)