Lines Matching defs:pBus
224 DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
247 PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
315 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
603 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
606 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
610 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
622 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
630 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
635 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
659 PPCIBUS pBus = &pGlobals->PciBus;
685 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
687 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
737 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
761 * @param pBus Pointer to the bus to search on.
764 DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
767 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
773 PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
1212 * @param pBus The bus to save.
1215 static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1220 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1222 PPCIDEVICE pDev = pBus->devices[i];
1441 * @param pBus The bus which data is being loaded.
1446 static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1462 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1464 PPCIDEVICE pDev = pBus->devices[i];
1488 if ( u32 >= RT_ELEMENTS(pBus->devices)
1498 if (pBus->devices[i])
1500 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1501 PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1504 i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1527 pDev = pBus->devices[i];
1560 PPCIBUS pBus = &pThis->PciBus;
1600 return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1610 * @param pBus The bus to register with.
1615 static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1627 && !pBus->devices[9])
1632 && !pBus->devices[0xf8])
1636 Assert(!(pBus->iDevSearch % 8));
1637 for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1638 if ( !pBus->devices[iDev]
1639 && !pBus->devices[iDev + 1]
1640 && !pBus->devices[iDev + 2]
1641 && !pBus->devices[iDev + 3]
1642 && !pBus->devices[iDev + 4]
1643 && !pBus->devices[iDev + 5]
1644 && !pBus->devices[iDev + 6]
1645 && !pBus->devices[iDev + 7])
1647 if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1668 //AssertReleaseMsg(iDev > 8 || pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1669 if (pBus->devices[iDev])
1673 iDev, pszName, pBus->devices[iDev]->name));
1674 if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1675 || (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1676 || (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1677 || (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1678 || (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1679 || (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1680 || (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1681 || (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1684 pszName, pBus->devices[iDev]->name, iDev));
1689 for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1691 if ( !pBus->devices[iDevRel]
1692 && !pBus->devices[iDevRel + 1]
1693 && !pBus->devices[iDevRel + 2]
1694 && !pBus->devices[iDevRel + 3]
1695 && !pBus->devices[iDevRel + 4]
1696 && !pBus->devices[iDevRel + 5]
1697 && !pBus->devices[iDevRel + 6]
1698 && !pBus->devices[iDevRel + 7])
1703 if (!pBus->devices[iDev + i])
1705 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1706 pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1707 pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1708 pBus->devices[iDev + i] = NULL;
1712 if (pBus->devices[iDev])
1721 Assert(!pBus->devices[iDev]);
1724 pPciDev->Int.s.pBusR3 = pBus;
1725 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1726 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1729 pBus->devices[iDev] = pPciDev;
1732 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1735 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1736 pBus->cBridges++;
1751 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1758 || iDev >= (int)RT_ELEMENTS(pBus->devices)
1768 return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1931 * @param pBus The bus to display.
1937 static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1939 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1941 PPCIDEVICE pPciDev = pBus->devices[iDev];
1951 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2029 if (pBus->cBridges > 0)
2032 pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2033 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2035 PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2047 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2050 pciR3BusInfo(pBus, pHlp, 0, false);
2052 pciR3BusInfo(pBus, pHlp, 0, true);
2066 PPCIBUS pBus = &pGlobals->PciBus;
2069 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2070 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2073 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2075 if (pBus->devices[i])
2076 pBus->devices[i]->Int.s.pBusRC += offDelta;
2147 PPCIBUS pBus = &pGlobals->PciBus;
2157 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2161 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2164 pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2166 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2167 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2177 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2178 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2179 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2180 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2181 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2182 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2184 pBus->PciDev.pDevIns = pDevIns;
2185 pciDevSetRequestedDevfunc(&pBus->PciDev);
2186 pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2197 pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2200 pBus->iDevSearch = 16;
2230 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
2319 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2327 uDevFnBridge = pBus->PciDev.devfn;
2331 pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2332 pPciDevBus = &pBus->PciDev;
2333 } while (pBus->iBus != 0);
2335 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2336 pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2346 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2351 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2353 PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2363 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2378 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2384 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2386 PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2396 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2435 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2442 || iDev >= (int)RT_ELEMENTS(pBus->devices))
2451 return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2460 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2463 pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2464 pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2465 pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2474 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2475 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2478 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2480 if (pBus->devices[i])
2481 pBus->devices[i]->Int.s.pBusRC += offDelta;
2517 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2518 pBus->pDevInsR3 = pDevIns;
2519 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2520 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2521 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->devices));
2533 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2537 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2540 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2542 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2543 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2548 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2549 PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2550 PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2551 PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2552 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2553 PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2554 PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2555 PCIDevSetCommand( &pBus->PciDev, 0x00);
2556 PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2557 PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2563 PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2565 pBus->PciDev.pDevIns = pDevIns;
2568 pciDevSetPci2PciBridge(&pBus->PciDev);
2569 pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2570 pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2575 rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2579 pBus->iDevSearch = 0;
2588 pBus->iBus = iInstance + 1;
2594 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",