Lines Matching defs:PciDev

105     PCIDEVICE           PciDev;
2177 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2178 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2179 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2180 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2181 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2182 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2184 pBus->PciDev.pDevIns = pDevIns;
2185 pciDevSetRequestedDevfunc(&pBus->PciDev);
2186 pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2327 uDevFnBridge = pBus->PciDev.devfn;
2331 pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2332 pPciDevBus = &pBus->PciDev;
2351 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2384 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2463 pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2464 pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2465 pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2548 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2549 PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2550 PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2551 PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2552 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2553 PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2554 PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2555 PCIDevSetCommand( &pBus->PciDev, 0x00);
2556 PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2557 PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2563 PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2565 pBus->PciDev.pDevIns = pDevIns;
2568 pciDevSetPci2PciBridge(&pBus->PciDev);
2569 pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2570 pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2575 rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);