Cross Reference: /vbox/src/VBox/Devices/Audio/DevIchHda.cpp

Lines Matching refs:PciDev
618     PCIDevice                          PciDev;
3079     PHDASTATE   pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3715     PCIDevSetVendorId           (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3716     PCIDevSetDeviceId           (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3718     PCIDevSetCommand            (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3719     PCIDevSetStatus             (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3720     PCIDevSetRevisionId         (&pThis->PciDev, 0x01);   /* 08 ro - rid. */
3721     PCIDevSetClassProg          (&pThis->PciDev, 0x00);   /* 09 ro - pi. */
3722     PCIDevSetClassSub           (&pThis->PciDev, 0x03);   /* 0a ro - scc; 03 == HDA. */
3723     PCIDevSetClassBase          (&pThis->PciDev, 0x04);   /* 0b ro - bcc; 04 == multimedia. */
3724     PCIDevSetHeaderType         (&pThis->PciDev, 0x00);   /* 0e ro - headtyp. */
3725     PCIDevSetBaseAddress        (&pThis->PciDev, 0,       /* 10 rw - MMIO */
3727     PCIDevSetInterruptLine      (&pThis->PciDev, 0x00);   /* 3c rw. */
3728     PCIDevSetInterruptPin       (&pThis->PciDev, 0x01);   /* 3d ro - INTA#. */
3731     PCIDevSetCapabilityList     (&pThis->PciDev, 0x80);
3733     PCIDevSetCapabilityList     (&pThis->PciDev, 0x60);
3735     PCIDevSetCapabilityList     (&pThis->PciDev, 0x50);   /* ICH6 datasheet 18.1.16 */
3741     PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3744     PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3745     PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3746     PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3750     PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3751     PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3753     PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3758     PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3760     PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3762     PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3764     PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3766     PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3768     PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3770     PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3772     PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3774     PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3776     PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3778     PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3780     PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3782     PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3784     PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3786     PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3788     PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3794     rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3812         PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3913         PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3914         PCIDevSetSubSystemId(      &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */