Lines Matching defs:SR_DCH
80 #define SR_DCH RT_BIT(0) /* ro, controller halted */
83 #define SR_RO_MASK (SR_DCH | SR_CELV)
515 ichac97UpdateStatus(pThis, pReg, SR_DCH);
1396 if (pReg->sr & SR_DCH) /* Controller halted? */
1431 pReg->sr |= SR_DCH; /* CELV? */
1499 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1722 if ((pReg->cr & CR_RPBM) && (pReg->sr & SR_DCH))
1724 pReg->sr &= ~(SR_DCH | SR_CELV);
1745 pReg->sr |= SR_DCH;
1752 pReg->sr &= ~SR_DCH;