Lines Matching defs:cg
515 } cg;
692 #define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
693 #define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
694 #define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
695 #define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
696 #define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
697 #define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
698 #define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
699 #define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
700 #define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
701 #define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
702 #define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
703 #define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
704 #define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
705 #define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1