Lines Matching defs:cfgspc
658 pciCfgSpc cfgspc;
676 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
677 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
678 #define pci_device cfgspc.regs.dv_id.dv.device
679 #define pci_status_command cfgspc.regs.stat_cmd.status_command
680 #define pci_command cfgspc.regs.stat_cmd.sc.command
681 #define pci_status cfgspc.regs.stat_cmd.sc.status
682 #define pci_class_revision cfgspc.regs.class_rev.class_revision
683 #define pci_rev_id cfgspc.regs.class_rev.cr.rev_id
684 #define pci_prog_if cfgspc.regs.class_rev.cr.prog_if
685 #define pci_sub_class cfgspc.regs.class_rev.cr.sub_class
686 #define pci_base_class cfgspc.regs.class_rev.cr.base_class
687 #define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache
688 #define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size
689 #define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer
690 #define pci_header_type cfgspc.regs.bhlc.bhlc.header_type
691 #define pci_bist cfgspc.regs.bhlc.bhlc.bist
692 #define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
693 #define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
694 #define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
695 #define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
696 #define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
697 #define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
698 #define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
699 #define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
700 #define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
701 #define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
702 #define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
703 #define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
704 #define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
705 #define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1
706 #define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
707 #define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
708 #define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
709 #define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
710 #define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
711 #define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
712 #define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr
713 #define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor
714 #define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor
715 #define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card
716 #define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom
717 #define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
718 #define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
719 #define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
720 #define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
721 #define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
722 #define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
723 #define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
724 #define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
725 #define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
726 #define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
727 #define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
728 #define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit
729 #define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1
730 #define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2
731 #define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base
732 #define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit
733 #define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase
734 #define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit
735 #define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line
736 #define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin
737 #define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt
738 #define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat
739 #define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline
740 #define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control
741 #define pci_user_config cfgspc.regs.devspf.dwords[0]
742 #define pci_user_config_0 cfgspc.regs.devspf.bytes[0]
743 #define pci_user_config_1 cfgspc.regs.devspf.bytes[1]
744 #define pci_user_config_2 cfgspc.regs.devspf.bytes[2]
745 #define pci_user_config_3 cfgspc.regs.devspf.bytes[3]