Lines Matching defs:bc
571 } bc;
708 #define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
709 #define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
710 #define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
711 #define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
712 #define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
713 #define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
719 #define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
720 #define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
721 #define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
722 #define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
723 #define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
724 #define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
725 #define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
726 #define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
727 #define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
728 #define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
729 #define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
730 #define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit