Lines Matching refs:pCtl
130 static void vboxCmdVbvaCtlFree(PHGSMIGUESTCOMMANDCONTEXT pHGSMICtx, VBOXCMDVBVA_CTL * pCtl)
132 VBoxSHGSMICommandFree(&pHGSMICtx->heapCtx, pCtl);
135 static int vboxCmdVbvaCtlSubmitSync(PHGSMIGUESTCOMMANDCONTEXT pHGSMICtx, VBOXCMDVBVA_CTL * pCtl)
137 const VBOXSHGSMIHEADER* pHdr = VBoxSHGSMICommandPrepSynch(&pHGSMICtx->heapCtx, pCtl);
158 rc = pCtl->i32Result;
160 WARN(("pCtl->i32Result %d", pCtl->i32Result));
175 static int vboxCmdVbvaCtlSubmitAsync(PHGSMIGUESTCOMMANDCONTEXT pHGSMICtx, VBOXCMDVBVA_CTL * pCtl, FNVBOXSHGSMICMDCOMPLETION pfnCompletion, void *pvCompletion)
177 const VBOXSHGSMIHEADER* pHdr = VBoxSHGSMICommandPrepAsynch(&pHGSMICtx->heapCtx, pCtl, pfnCompletion, pvCompletion, VBOXSHGSMI_FLAG_GH_ASYNCH_IRQ);
202 VBOXCMDVBVA_CTL_ENABLE *pCtl = (VBOXCMDVBVA_CTL_ENABLE*)vboxCmdVbvaCtlCreate(pHGSMICtx, sizeof (*pCtl));
203 if (!pCtl)
209 pCtl->Hdr.u32Type = VBOXCMDVBVACTL_TYPE_ENABLE;
210 pCtl->Hdr.i32Result = VERR_NOT_IMPLEMENTED;
211 memset(&pCtl->Enable, 0, sizeof (pCtl->Enable));
212 pCtl->Enable.u32Flags = fEnable? VBVA_F_ENABLE: VBVA_F_DISABLE;
213 pCtl->Enable.u32Offset = pCtx->offVRAMBuffer;
214 pCtl->Enable.i32Result = VERR_NOT_SUPPORTED;
215 pCtl->Enable.u32Flags |= VBVA_F_ABSOFFSET;
217 int rc = vboxCmdVbvaCtlSubmitSync(pHGSMICtx, &pCtl->Hdr);
220 rc = pCtl->Hdr.i32Result;
227 vboxCmdVbvaCtlFree(pHGSMICtx, &pCtl->Hdr);