Cross Reference: /vbox/include/iprt/x86.h

Lines Matching defs:Intel
351     /** Bit 23 - MMX - Intel MMX 'Technology'. */
507 /** Bit 23 - MMX - Intel MMX Technology. */
564 /** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
578 /** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
609 /** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
651 /** Bit 23 - MMX - Intel MMX Technology. */
1082 /** Get FSB clock status (Intel-specific). */
1085 /** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1122 /** Performance counter MSRs. (Intel only) */
1131 /** Performance state value and starting with Intel core more.
1149 /** Enhanced Intel SpeedStep Technology Enable (R/W). */
1782  * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2643  * Intel MPX bound registers state (XSAVE_C_BNDREGS).
2665  * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2766         } Intel;
2779          * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
2785 AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
2787 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi,      0x240);
2788 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs,    0x340);
2789 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg,     0x380);
2790 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask,     0x440 /* 1088 */);
2791 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256,   0x480 /* 1152 */);
2792 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi,    0x680 /* 1664 */);
2854     /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */