Lines Matching refs:VMMR0_INT_DECL
172 VMMR0_INT_DECL(int) HMR0Init(void);
173 VMMR0_INT_DECL(int) HMR0Term(void);
174 VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
175 VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
176 VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
177 VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
178 VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
180 VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
182 VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
197 VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
198 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
199 VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
200 VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
201 VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
202 VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
203 VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
206 VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
207 VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
208 VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
211 VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx);