Cross Reference: /solaris-x11-s12/open-src/kernel/mdb/modules/i915.c

Lines Matching defs:val
662 i915_read(struct drm_i915_private *dev_priv, uintptr_t addr, uint32_t *val)
674 	if (mdb_pread(val, sizeof (uint32_t),
698 	uint32_t val;
709 	ret = i915_read(dev_priv, addr, &val);
714 	mdb_printf("Register [0x%x]: 0x%x\n", addr, val);
746 	uint32_t val;
764 	ret = i915_read(dev_priv, (uintptr_t)PGTBL_ER, &val);
766 		mdb_printf("PGTBL_ER: 0x%lx\n", val);
768 	ret = i915_read(dev_priv, (uintptr_t)INSTPM, &val);
770 		mdb_printf("INSTPM: 0x%lx\n", val);
772 	ret = i915_read(dev_priv, (uintptr_t)EIR, &val);
774 		mdb_printf("EIR: 0x%lx\n", val);
776 	ret = i915_read(dev_priv, (uintptr_t)ERROR_GEN6, &val);
778 		mdb_printf("ERROR_GEN6: 0x%lx\n", val);
781 	ret = i915_read(dev_priv, (uintptr_t)0x22064, &val);
783 		mdb_printf("  BLT EIR: 0x%08x\n", val);
785 	ret = i915_read(dev_priv, (uintptr_t)0x22068, &val);
787 		mdb_printf("  BLT EHR: 0x%08x\n", val);
789 	ret = i915_read(dev_priv, (uintptr_t)0x2206C, &val);
791 		mdb_printf("  INSTDONE: 0x%08x\n", val);
793 	ret = i915_read(dev_priv, (uintptr_t)0x22074, &val);
795 		mdb_printf("  ACTHD: 0x%08x\n", val);
799 	ret = i915_read(dev_priv, (uintptr_t)IPEIR_I965, &val);
801 		mdb_printf("  RENDER EIR: 0x%08x\n", val);
803 	ret = i915_read(dev_priv, (uintptr_t)IPEHR_I965, &val);
805 		mdb_printf("  RENDER EHR: 0x%08x\n", val);
807 	ret = i915_read(dev_priv, (uintptr_t)INSTDONE_I965, &val);
809 		mdb_printf("  INSTDONE: 0x%08x\n", val);
811 	ret = i915_read(dev_priv, (uintptr_t)INSTPS, &val);
813 		mdb_printf("  INSTPS: 0x%08x\n", val);
815 	ret = i915_read(dev_priv, (uintptr_t)INSTDONE1, &val);
817 		mdb_printf("  INSTDONE1: 0x%08x\n", val);
819 	ret = i915_read(dev_priv, (uintptr_t)ACTHD_I965, &val);
821 		mdb_printf("  ACTHD: 0x%08x\n", val);
823 	ret = i915_read(dev_priv, (uintptr_t)0x2078, &val);
825 		mdb_printf("  DMA_FADD_P: 0x%08x\n", val);
827 	ret = i915_read(dev_priv, (uintptr_t)0x04094, &val);
829 		mdb_printf("\nGraphics Engine Fault 0x%lx\n", val);
831 	ret = i915_read(dev_priv, (uintptr_t)0x04194, &val);
833 		mdb_printf("Media Engine Fault 0x%lx\n", val);
835 	ret = i915_read(dev_priv, (uintptr_t)0x04294, &val);
837 		mdb_printf("Blitter  Engine Fault 0x%lx\n", val);
1382 	uint32_t val;
1408 		ret = i915_read(dev_priv, (uintptr_t)VLV_IER, &val);
1410 			mdb_printf("Display IER:\t%08x\n", val);
1412 		ret = i915_read(dev_priv, (uintptr_t)VLV_IIR, &val);
1414 			mdb_printf("Display IIR:\t%08x\n", val);
1416 		ret = i915_read(dev_priv, (uintptr_t)VLV_IIR_RW, &val);
1418 			mdb_printf("Display IIR_RW:\t%08x\n", val);
1420 		ret = i915_read(dev_priv, (uintptr_t)VLV_IMR, &val);
1422 			mdb_printf("Display IMR:\t%08x\n", val);
1425 			ret = i915_read(dev_priv, PIPESTAT(pipe), &val);
1428 				    pipe_name(pipe), val);
1430 		ret = i915_read(dev_priv, (uintptr_t)VLV_MASTER_IER, &val);
1432 			mdb_printf("Master IER:\t%08x\n", val);
1434 		ret = i915_read(dev_priv, (uintptr_t)GTIER, &val);
1436 			mdb_printf("Render IER:\t%08x\n", val);
1438 		ret = i915_read(dev_priv, (uintptr_t)GTIIR, &val);
1440 			mdb_printf("Render IIR:\t%08x\n", val);
1442 		ret = i915_read(dev_priv, (uintptr_t)GTIMR, &val);
1444 			mdb_printf("Render IMR:\t%08x\n", val);
1446 		ret = i915_read(dev_priv, (uintptr_t)GEN6_PMIER, &val);
1448 			mdb_printf("PM IER:\t\t%08x\n", val);
1450 		ret = i915_read(dev_priv, (uintptr_t)GEN6_PMIIR, &val);
1452 			mdb_printf("PM IIR:\t\t%08x\n", val);
1454 		ret = i915_read(dev_priv, (uintptr_t)GEN6_PMIMR, &val);
1456 			mdb_printf("PM IMR:\t\t%08x\n", val);
1458 		ret = i915_read(dev_priv, (uintptr_t)PORT_HOTPLUG_EN, &val);
1460 			mdb_printf("Port hotplug:\t%08x\n", val);
1462 		ret = i915_read(dev_priv, (uintptr_t)VLV_DPFLIPSTAT, &val);
1464 			mdb_printf("DPFLIPSTAT:\t%08x\n", val);
1466 		ret = i915_read(dev_priv, (uintptr_t)DPINVGTT, &val);
1468 			mdb_printf("DPINVGTT:\t%08x\n", val);
1470 		ret = i915_read(dev_priv, (uintptr_t)IER, &val);
1472 			mdb_printf("Interrupt enable:    %08x\n", val);
1474 		ret = i915_read(dev_priv, (uintptr_t)IIR, &val);
1476 			mdb_printf("Interrupt identity:  %08x\n", val);
1478 		ret = i915_read(dev_priv, (uintptr_t)IMR, &val);
1480 			mdb_printf("Interrupt mask:      %08x\n", val);
1484 			    &val);
1487 				    pipe_name(pipe), val);
1490 		ret = i915_read(dev_priv, (uintptr_t)DEIER, &val);
1494 			    val);
1496 		ret = i915_read(dev_priv, (uintptr_t)DEIIR, &val);
1499 			    "North Display Interrupt identity:	%08x\n", val);
1501 		ret = i915_read(dev_priv, (uintptr_t)DEIMR, &val);
1505 			    val);
1507 		ret = i915_read(dev_priv, (uintptr_t)SDEIER, &val);
1511 			    val);
1513 		ret = i915_read(dev_priv, (uintptr_t)SDEIIR, &val);
1516 			    "South Display Interrupt identity:	%08x\n", val);
1518 		ret = i915_read(dev_priv, (uintptr_t)SDEIMR, &val);
1522 			    val);
1524 		ret = i915_read(dev_priv, (uintptr_t)GTIER, &val);
1527 			    "Graphics Interrupt enable:		%08x\n", val);
1529 		ret = i915_read(dev_priv, (uintptr_t)GTIIR, &val);
1533 			    val);
1535 		ret = i915_read(dev_priv, (uintptr_t)GTIMR, &val);
1538 			    "Graphics Interrupt mask:		%08x\n", val);
1617 	uint32_t val;
1648 		ret = i915_read(dev_priv, (uintptr_t)ILK_DPFC_CONTROL, &val);
1650 			val &= DPFC_CTL_EN;
1656 		ret = i915_read(dev_priv, (uintptr_t)DPFC_CONTROL, &val);
1658 			val &= DPFC_CTL_EN;
1664 		ret = i915_read(dev_priv, (uintptr_t)FBC_CONTROL, &val);
1666 			val &= FBC_CTL_EN;
1673 	if (val) {
1724 	uint32_t val = 0;
1750 		ret = i915_read(dev_priv, (uintptr_t)WM1_LP_ILK, &val);
1752 			val &= WM1_LP_SR_EN;
1758 		ret = i915_read(dev_priv, (uintptr_t)FW_BLC_SELF, &val);
1760 			val &= FW_BLC_SELF_EN;
1766 		ret = i915_read(dev_priv, (uintptr_t)INSTPM, &val);
1768 			val &= INSTPM_SELF_EN;
1774 		ret = i915_read(dev_priv, (uintptr_t)DSPFW3, &val);
1776 			val &= PINEVIEW_SELF_REFRESH_EN;
1784 	    val ? "enabled" : "disabled");
1932 	uint32_t val = 0;
1963 		ret = i915_read(dev_priv, (uintptr_t)DCC, &val);
1965 			mdb_printf("DDC = 0x%08x\n", val);
1967 		ret = i915_read(dev_priv, (uintptr_t)C0DRB3, &val);
1969 			mdb_printf("C0DRB3 = 0x%04x\n", val);
1971 		ret = i915_read(dev_priv, (uintptr_t)C1DRB3, &val);
1973 			mdb_printf("C1DRB3 = 0x%04x\n", val);
1976 		ret = i915_read(dev_priv, (uintptr_t)MAD_DIMM_C0, &val);
1978 			mdb_printf("MAD_DIMM_C0 = 0x%08x\n", val);
1980 		ret = i915_read(dev_priv, (uintptr_t)MAD_DIMM_C1, &val);
1982 			mdb_printf("MAD_DIMM_C1 = 0x%08x\n", val);
1984 		ret = i915_read(dev_priv, (uintptr_t)MAD_DIMM_C2, &val);
1986 			mdb_printf("MAD_DIMM_C2 = 0x%08x\n", val);
1988 		ret = i915_read(dev_priv, (uintptr_t)TILECTL, &val);
1990 			mdb_printf("TILECTL = 0x%08x\n", val);
1992 		ret = i915_read(dev_priv, (uintptr_t)ARB_MODE, &val);
1994 			mdb_printf("ARB_MODE = 0x%08x\n", val);
1996 		ret = i915_read(dev_priv, (uintptr_t)DISP_ARB_CTL, &val);
1998 			mdb_printf("DISP_ARB_CTL = 0x%08x\n", val);
2028 	uint32_t val = 0;
2054 		ret = i915_read(dev_priv, (uintptr_t)GFX_MODE, &val);
2056 			mdb_printf("GFX_MODE: 0x%08x\n", val);
2064 			    &val);
2066 				mdb_printf("GFX_MODE: 0x%08x\n", val);
2069 		    (uintptr_t)(dev_priv->ring[i].mmio_base + 0x228), &val);
2071 			mdb_printf("PP_DIR_BASE: 0x%08x\n", val);
2074 		    (uintptr_t)(dev_priv->ring[i].mmio_base + 0x518), &val);
2076 			mdb_printf("PP_DIR_BASE_READ: 0x%08x\n", val);
2079 		    (uintptr_t)(dev_priv->ring[i].mmio_base + 0x220), &val);
2081 			mdb_printf("PP_DIR_DCLV: 0x%08x\n", val);
2097 	ret = i915_read(dev_priv, (uintptr_t)GAM_ECOCHK, &val);
2099 		mdb_printf("ECOCHK: 0x%08x\n", val);