Cross Reference: /solaris-x11-s12/open-src/kernel/i915/src/intel

Lines Matching refs:rps
3038 	if (*val >= dev_priv->rps.max_delay)
3039 		*val = dev_priv->rps.max_delay;
3040 	limits |= dev_priv->rps.max_delay << 24;
3048 	if (*val <= dev_priv->rps.min_delay) {
3049 		*val = dev_priv->rps.min_delay;
3050 		limits |= dev_priv->rps.min_delay << 16;
3061 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3062 	WARN_ON(val > dev_priv->rps.max_delay);
3063 	WARN_ON(val < dev_priv->rps.min_delay);
3065 	if (val == dev_priv->rps.cur_delay)
3084 	dev_priv->rps.cur_delay = (u8)val;
3097 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3110 	if (pval != dev_priv->rps.cur_delay)
3112 				 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3113 				 dev_priv->rps.cur_delay,
3116 	dev_priv->rps.cur_delay = (u8)pval;
3125 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3126 	WARN_ON(val > dev_priv->rps.max_delay);
3127 	WARN_ON(val < dev_priv->rps.min_delay);
3133 				      dev_priv->rps.cur_delay),
3134 			 dev_priv->rps.cur_delay,
3137 	if (val == dev_priv->rps.cur_delay)
3142 	dev_priv->rps.cur_delay = val;
3154 	/* Complete PM interrupt masking here doesn't race with the rps work
3159 	spin_lock_irq(&dev_priv->rps.lock);
3160 	dev_priv->rps.pm_iir = 0;
3161 	spin_unlock_irq(&dev_priv->rps.lock);
3173 	/* Complete PM interrupt masking here doesn't race with the rps work
3178 	spin_lock_irq(&dev_priv->rps.lock);
3179 	dev_priv->rps.pm_iir = 0;
3180 	spin_unlock_irq(&dev_priv->rps.lock);
3226 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3248 	dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3249 	dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3250 	dev_priv->rps.cur_delay = 0;
3310 		   dev_priv->rps.max_delay << 24 |
3311 		   dev_priv->rps.min_delay << 16);
3333 					 (dev_priv->rps.max_delay & 0xff) * 50,
3335 			dev_priv->rps.hw_max = pcu_mbox & 0xff;
3345 	spin_lock_irq(&dev_priv->rps.lock);
3347 	 * dev_priv->rps.pm_iir really should be 0 here. */
3348 	dev_priv->rps.pm_iir = 0;
3351 	spin_unlock_irq(&dev_priv->rps.lock);
3380 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3396 	for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3398 		int diff = dev_priv->rps.max_delay - gpu_freq;
3461 						    rps.vlv_work.work);
3470 	mutex_lock(&dev_priv->rps.hw_lock);
3471 	if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3472 		valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3473 	mutex_unlock(&dev_priv->rps.hw_lock);
3525 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3583 	dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3586 				      dev_priv->rps.cur_delay),
3587 			 dev_priv->rps.cur_delay);
3589 	dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3590 	dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3593 				      dev_priv->rps.max_delay),
3594 			 dev_priv->rps.max_delay);
3596 	dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3599 				      dev_priv->rps.rpe_delay),
3600 			 dev_priv->rps.rpe_delay);
3602 	dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3605 				      dev_priv->rps.min_delay),
3606 			 dev_priv->rps.min_delay);
3610 				      dev_priv->rps.rpe_delay),
3611 			 dev_priv->rps.rpe_delay);
3613 	//INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3615 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3619 	spin_lock_irq(&dev_priv->rps.lock);
3620 	WARN_ON(dev_priv->rps.pm_iir != 0);
3622 	spin_unlock_irq(&dev_priv->rps.lock);
3857 		del_timer_sync(&dev_priv->rps.delayed_resume_timer);
3859 //			cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3860 		mutex_lock(&dev_priv->rps.hw_lock);
3865 		mutex_unlock(&dev_priv->rps.hw_lock);
3872 						rps.delayed_resume_work);
3875 	mutex_lock(&dev_priv->rps.hw_lock);
3883 	mutex_unlock(&dev_priv->rps.hw_lock);
3891 	(void) queue_work(dev_priv->wq, &dev_priv->rps.delayed_resume_work);
3907 		test_set_timer(&dev_priv->rps.delayed_resume_timer, DRM_HZ);
5071 	INIT_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work);
5072 	setup_timer(&dev_priv->rps.delayed_resume_timer, intel_gen6_powersave_work_timer,
5078 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5102 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));