Lines Matching refs:I915_WRITE
69 I915_WRITE(FBC_CONTROL, fbc_ctl);
102 I915_WRITE(FBC_TAG + (i * 4), 0);
107 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
108 I915_WRITE(FBC_FENCE_OFF, crtc->y);
117 I915_WRITE(FBC_CONTROL, fbc_ctl);
144 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
146 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
149 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
189 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
194 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
217 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
219 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
222 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
223 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
225 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
228 I915_WRITE(SNB_DPFC_CTL_SA,
230 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
246 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
250 I915_WRITE(ILK_DSPCLK_GATE_D,
256 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
280 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset);
282 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
288 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
290 I915_WRITE(ILK_DSPCLK_GATE_D,
295 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
303 I915_WRITE(SNB_DPFC_CTL_SA,
305 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
793 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
1121 I915_WRITE(DSPFW1, reg);
1131 I915_WRITE(DSPFW3, reg);
1140 I915_WRITE(DSPFW3, reg);
1149 I915_WRITE(DSPFW3, reg);
1153 I915_WRITE(DSPFW3,
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1405 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1407 I915_WRITE(FW_BLC_SELF_VLV,
1417 I915_WRITE(DSPFW1,
1422 I915_WRITE(DSPFW2,
1425 I915_WRITE(DSPFW3,
1456 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1458 I915_WRITE(FW_BLC_SELF,
1468 I915_WRITE(DSPFW1,
1473 I915_WRITE(DSPFW2,
1477 I915_WRITE(DSPFW3,
1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1532 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1540 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1542 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1544 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1605 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1607 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1632 I915_WRITE(FW_BLC_SELF,
1635 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648 I915_WRITE(FW_BLC, fwater_lo);
1649 I915_WRITE(FW_BLC2, fwater_hi);
1654 I915_WRITE(FW_BLC_SELF,
1657 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1683 I915_WRITE(FW_BLC, fwater_lo);
1711 I915_WRITE(DISP_ARB_CTL,
1716 I915_WRITE(DISP_ARB_CTL,
1807 I915_WRITE(WM0_PIPEA_ILK,
1821 I915_WRITE(WM0_PIPEB_ILK,
1833 I915_WRITE(WM3_LP_ILK, 0);
1834 I915_WRITE(WM2_LP_ILK, 0);
1835 I915_WRITE(WM1_LP_ILK, 0);
1849 I915_WRITE(WM1_LP_ILK,
1864 I915_WRITE(WM2_LP_ILK,
1892 I915_WRITE(WM0_PIPEA_ILK, val |
1906 I915_WRITE(WM0_PIPEB_ILK, val |
1924 I915_WRITE(WM3_LP_ILK, 0);
1925 I915_WRITE(WM2_LP_ILK, 0);
1926 I915_WRITE(WM1_LP_ILK, 0);
1941 I915_WRITE(WM1_LP_ILK,
1956 I915_WRITE(WM2_LP_ILK,
1971 I915_WRITE(WM3_LP_ILK,
1995 I915_WRITE(WM0_PIPEA_ILK, val |
2009 I915_WRITE(WM0_PIPEB_ILK, val |
2023 I915_WRITE(WM0_PIPEC_IVB, val |
2041 I915_WRITE(WM3_LP_ILK, 0);
2042 I915_WRITE(WM2_LP_ILK, 0);
2043 I915_WRITE(WM1_LP_ILK, 0);
2058 I915_WRITE(WM1_LP_ILK,
2073 I915_WRITE(WM2_LP_ILK,
2093 I915_WRITE(WM3_LP_ILK,
2556 I915_WRITE(WM3_LP_ILK, 0);
2558 I915_WRITE(WM2_LP_ILK, 0);
2560 I915_WRITE(WM1_LP_ILK, 0);
2563 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2565 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2567 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2570 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2572 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2574 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2582 I915_WRITE(WM_MISC, val);
2591 I915_WRITE(DISP_ARB_CTL, val);
2595 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2597 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2599 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2602 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2604 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2606 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2769 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2783 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2799 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2811 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2946 I915_WRITE(RCUPEI, 100000);
2947 I915_WRITE(RCDNEI, 100000);
2950 I915_WRITE(RCBMAXAVG, 90000);
2951 I915_WRITE(RCBMINAVG, 80000);
2953 I915_WRITE(MEMIHYST, 1);
2974 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2980 I915_WRITE(VIDSTART, vstart);
2984 I915_WRITE(MEMMODECTL, rgvmodectl);
3011 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3012 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3013 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3014 I915_WRITE(DEIIR, DE_PCU_EVENT);
3015 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3021 I915_WRITE(MEMSWCTL, rgvswctl);
3069 I915_WRITE(GEN6_RPNSWREQ,
3072 I915_WRITE(GEN6_RPNSWREQ,
3080 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3150 I915_WRITE(GEN6_RC_CONTROL, 0);
3151 I915_WRITE(GEN6_RPNSWREQ, 1UL << 31);
3152 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3153 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3163 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3170 I915_WRITE(GEN6_RC_CONTROL, 0);
3171 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3172 I915_WRITE(GEN6_PMIER, 0);
3182 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3234 I915_WRITE(GEN6_RC_STATE, 0);
3239 I915_WRITE(GTFIFODBG, gtfifodbg);
3253 I915_WRITE(GEN6_RC_CONTROL, 0);
3255 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3256 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3257 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3258 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3259 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3262 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3264 I915_WRITE(GEN6_RC_SLEEP, 0);
3265 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3266 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3267 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3268 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3289 I915_WRITE(GEN6_RC_CONTROL,
3295 I915_WRITE(GEN6_RPNSWREQ,
3297 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3300 I915_WRITE(GEN6_RPNSWREQ,
3304 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3308 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3309 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3313 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3314 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3315 I915_WRITE(GEN6_RP_UP_EI, 66000);
3316 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3318 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3319 I915_WRITE(GEN6_RP_CONTROL,
3344 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
3349 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3350 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3353 I915_WRITE(GEN6_PMINTRMSK, 0);
3512 I915_WRITE(VLV_PCBR, pctx_paddr);
3529 I915_WRITE(GTFIFODBG, gtfifodbg);
3536 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3537 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3538 I915_WRITE(GEN6_RP_UP_EI, 66000);
3539 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3541 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3543 I915_WRITE(GEN6_RP_CONTROL,
3551 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3552 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3553 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3556 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3558 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3561 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3562 I915_WRITE(GEN6_RC_CONTROL,
3618 I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
3621 I915_WRITE(GEN6_PMIMR, 0);
3624 I915_WRITE(GEN6_PMINTRMSK, 0);
3652 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3656 I915_WRITE(PWRCTXA, 0);
3659 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3741 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3742 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3782 I915_WRITE(ECR, 0);
3786 I915_WRITE(SDEW, 0x15040d00);
3787 I915_WRITE(CSIEW0, 0x007f0000);
3788 I915_WRITE(CSIEW1, 0x1e220004);
3789 I915_WRITE(CSIEW2, 0x04000004);
3792 I915_WRITE(PEW + (i * 4), 0);
3794 I915_WRITE(DEW + (i * 4), 0);
3819 I915_WRITE(PXW + (i * 4), val);
3823 I915_WRITE(OGW0, 0);
3824 I915_WRITE(OGW1, 0);
3825 I915_WRITE(EG0, 0x00007f00);
3826 I915_WRITE(EG1, 0x0000000e);
3827 I915_WRITE(EG2, 0x000e0000);
3828 I915_WRITE(EG3, 0x68000300);
3829 I915_WRITE(EG4, 0x42000000);
3830 I915_WRITE(EG5, 0x00140031);
3831 I915_WRITE(EG6, 0);
3832 I915_WRITE(EG7, 0);
3835 I915_WRITE(PXWL + (i * 4), 0);
3838 I915_WRITE(ECR, 0x80000019);
3920 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3929 I915_WRITE(DSPCNTR(pipe),
3946 I915_WRITE(PCH_3DCGDIS0,
3949 I915_WRITE(PCH_3DCGDIS1,
3959 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3963 I915_WRITE(DISP_ARB_CTL,
3966 I915_WRITE(WM3_LP_ILK, 0);
3967 I915_WRITE(WM2_LP_ILK, 0);
3968 I915_WRITE(WM1_LP_ILK, 0);
3978 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3981 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3986 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3988 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3991 I915_WRITE(_3D_CHICKEN2,
3996 I915_WRITE(CACHE_MODE_0,
4015 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4016 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4030 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4034 I915_WRITE(TRANS_CHICKEN1(pipe),
4057 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4059 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4064 I915_WRITE(_3D_CHICKEN,
4069 I915_WRITE(GEN6_GT_MODE,
4072 I915_WRITE(WM3_LP_ILK, 0);
4073 I915_WRITE(WM2_LP_ILK, 0);
4074 I915_WRITE(WM1_LP_ILK, 0);
4076 I915_WRITE(CACHE_MODE_0,
4079 I915_WRITE(GEN6_UCGCTL1,
4097 I915_WRITE(GEN6_UCGCTL2,
4103 I915_WRITE(_3D_CHICKEN3, (0xFFFFUL << 16) |
4115 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4118 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4121 I915_WRITE(ILK_DSPCLK_GATE_D,
4127 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4134 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffffUL));
4135 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4154 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4166 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4171 I915_WRITE(_TRANSA_CHICKEN1,
4184 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4192 I915_WRITE(WM3_LP_ILK, 0);
4193 I915_WRITE(WM2_LP_ILK, 0);
4194 I915_WRITE(WM1_LP_ILK, 0);
4199 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4202 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4206 I915_WRITE(GEN7_L3CNTLREG1,
4208 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4212 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4222 I915_WRITE(CACHE_MODE_1,
4226 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4230 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4233 I915_WRITE(CHICKEN_PAR1_1,
4244 I915_WRITE(WM3_LP_ILK, 0);
4245 I915_WRITE(WM2_LP_ILK, 0);
4246 I915_WRITE(WM1_LP_ILK, 0);
4248 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4251 I915_WRITE(_3D_CHICKEN3,
4255 I915_WRITE(IVB_CHICKEN3,
4261 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4264 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4268 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4272 I915_WRITE(GEN7_L3CNTLREG1,
4274 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4277 I915_WRITE(GEN7_ROW_CHICKEN2,
4280 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4285 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4301 I915_WRITE(GEN6_UCGCTL2,
4306 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4313 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4320 I915_WRITE(CACHE_MODE_1,
4326 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4338 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4341 I915_WRITE(_3D_CHICKEN3,
4345 I915_WRITE(IVB_CHICKEN3,
4349 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4354 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4358 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4359 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4362 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4366 I915_WRITE(GEN7_ROW_CHICKEN2,
4370 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4375 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4395 I915_WRITE(GEN6_UCGCTL2,
4402 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4404 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4406 I915_WRITE(CACHE_MODE_1,
4414 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4417 I915_WRITE(0x9400, 0xffffffff);
4418 I915_WRITE(0x9404, 0xffffffff);
4419 I915_WRITE(0x9408, 0xffffffff);
4420 I915_WRITE(0x940c, 0xffffffff);
4421 I915_WRITE(0x9410, 0xffffffff);
4422 I915_WRITE(0x9414, 0xffffffff);
4423 I915_WRITE(0x9418, 0xffffffff);
4431 I915_WRITE(RENCLK_GATE_D1, 0);
4432 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4435 I915_WRITE(RAMCLK_GATE_D, 0);
4441 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4444 I915_WRITE(CACHE_MODE_0,
4454 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4455 I915_WRITE(RENCLK_GATE_D2, 0);
4456 I915_WRITE(DSPCLK_GATE_D, 0);
4457 I915_WRITE(RAMCLK_GATE_D, 0);
4459 I915_WRITE(MI_ARB_STATE,
4467 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4472 I915_WRITE(RENCLK_GATE_D2, 0);
4473 I915_WRITE(MI_ARB_STATE,
4484 I915_WRITE(D_STATE, dstate);
4487 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4490 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4497 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4504 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4565 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4578 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4689 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5085 I915_WRITE(GEN6_PCODE_DATA, *val);
5086 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5095 I915_WRITE(GEN6_PCODE_DATA, 0);
5109 I915_WRITE(GEN6_PCODE_DATA, val);
5110 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5118 I915_WRITE(GEN6_PCODE_DATA, 0);