Lines Matching +defs:val +defs:channel
88 DRM_ERROR("invalid max DP link bw val %x, using 1.62Gbps\n",
254 DRM_ERROR("eDP powered off while attempting aux channel communication.");
338 /* Try to wait for any previous AUX channel activity */
355 /* Load the send data into the aux channel data registers */
434 /* Write data to the aux channel in native mode */
467 /* Write a single byte to the aux channel in native mode */
475 /* read bytes from a native aux channel */
1012 * If the panel wasn't on, delay before accessing aux channel
1434 int channel = vlv_dport_to_channel(dport);
1436 vlv_wait_port_ready(dev_priv, channel);
1455 u32 val;
1457 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1458 val = 0;
1460 val |= (1<<21);
1462 val &= ~(1<<21);
1463 val |= 0x001000c4;
1464 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
2016 uint32_t val;
2021 val = I915_READ(DP_TP_CTL(port));
2022 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2023 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2024 I915_WRITE(DP_TP_CTL(port), val);
2133 /* channel equalization */
2148 /* channel eq pattern */
2401 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2636 uint64_t val)
2644 ret = drm_object_property_set_value(&connector->base, property, val);
2649 int i = (int)val;
2673 switch (val) {
2698 if (val == DRM_MODE_SCALE_NONE) {
2703 if (intel_connector->panel.fitting_mode == val) {
2707 intel_connector->panel.fitting_mode = (int) val;