Lines Matching refs:temp
2229 u32 reg, temp;
2233 temp = I915_READ(reg);
2235 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2236 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2238 temp &= ~FDI_LINK_TRAIN_NONE;
2239 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2241 I915_WRITE(reg, temp);
2244 temp = I915_READ(reg);
2246 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2247 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2249 temp &= ~FDI_LINK_TRAIN_NONE;
2250 temp |= FDI_LINK_TRAIN_NONE;
2252 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276 uint32_t temp;
2288 temp = I915_READ(SOUTH_CHICKEN1);
2289 temp &= ~FDI_BC_BIFURCATION_SELECT;
2291 I915_WRITE(SOUTH_CHICKEN1, temp);
2303 u32 reg, temp, tries;
2312 temp = I915_READ(reg);
2313 temp &= ~FDI_RX_SYMBOL_LOCK;
2314 temp &= ~FDI_RX_BIT_LOCK;
2315 I915_WRITE(reg, temp);
2321 temp = I915_READ(reg);
2322 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2323 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_PATTERN_1;
2326 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2329 temp = I915_READ(reg);
2330 temp &= ~FDI_LINK_TRAIN_NONE;
2331 temp |= FDI_LINK_TRAIN_PATTERN_1;
2332 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2344 temp = I915_READ(reg);
2345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347 if ((temp & FDI_RX_BIT_LOCK)) {
2349 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2358 temp = I915_READ(reg);
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_PATTERN_2;
2361 I915_WRITE(reg, temp);
2364 temp = I915_READ(reg);
2365 temp &= ~FDI_LINK_TRAIN_NONE;
2366 temp |= FDI_LINK_TRAIN_PATTERN_2;
2367 I915_WRITE(reg, temp);
2374 temp = I915_READ(reg);
2375 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2377 if (temp & FDI_RX_SYMBOL_LOCK) {
2378 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2404 u32 reg, temp, i, retry;
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_RX_SYMBOL_LOCK;
2411 temp &= ~FDI_RX_BIT_LOCK;
2412 I915_WRITE(reg, temp);
2419 temp = I915_READ(reg);
2420 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2421 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_PATTERN_1;
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2426 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2427 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2433 temp = I915_READ(reg);
2435 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2448 temp = I915_READ(reg);
2449 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450 temp |= snb_b_fdi_train_param[i];
2451 I915_WRITE(reg, temp);
2458 temp = I915_READ(reg);
2459 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2460 if (temp & FDI_RX_BIT_LOCK) {
2461 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2475 temp = I915_READ(reg);
2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_2;
2479 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2481 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2483 I915_WRITE(reg, temp);
2486 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_2;
2494 I915_WRITE(reg, temp);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 temp |= snb_b_fdi_train_param[i];
2504 I915_WRITE(reg, temp);
2511 temp = I915_READ(reg);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513 if (temp & FDI_RX_SYMBOL_LOCK) {
2514 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536 u32 reg, temp, i;
2541 temp = I915_READ(reg);
2542 temp &= ~FDI_RX_SYMBOL_LOCK;
2543 temp &= ~FDI_RX_BIT_LOCK;
2544 I915_WRITE(reg, temp);
2554 temp = I915_READ(reg);
2555 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2556 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2557 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2558 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2560 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2561 temp |= FDI_COMPOSITE_SYNC;
2562 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2568 temp = I915_READ(reg);
2569 temp &= ~FDI_LINK_TRAIN_AUTO;
2570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2572 temp |= FDI_COMPOSITE_SYNC;
2573 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2580 temp = I915_READ(reg);
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 temp |= snb_b_fdi_train_param[i];
2583 I915_WRITE(reg, temp);
2589 temp = I915_READ(reg);
2590 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2592 if (temp & FDI_RX_BIT_LOCK ||
2594 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2604 temp = I915_READ(reg);
2605 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2606 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2609 I915_WRITE(reg, temp);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2615 I915_WRITE(reg, temp);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2634 if (temp & FDI_RX_SYMBOL_LOCK) {
2635 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2651 u32 reg, temp;
2656 temp = I915_READ(reg);
2657 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2660 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2666 temp = I915_READ(reg);
2667 I915_WRITE(reg, temp | FDI_PCDCLK);
2674 temp = I915_READ(reg);
2675 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2676 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2688 u32 reg, temp;
2692 temp = I915_READ(reg);
2693 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2697 temp = I915_READ(reg);
2698 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2704 temp = I915_READ(reg);
2705 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2718 u32 reg, temp;
2722 temp = I915_READ(reg);
2723 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2727 temp = I915_READ(reg);
2728 temp &= ~(0x7 << 16);
2729 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2730 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2742 temp = I915_READ(reg);
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 I915_WRITE(reg, temp);
2748 temp = I915_READ(reg);
2750 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2751 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2753 temp &= ~FDI_LINK_TRAIN_NONE;
2754 temp |= FDI_LINK_TRAIN_PATTERN_1;
2757 temp &= ~(0x07 << 16);
2758 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2759 I915_WRITE(reg, temp);
2811 u32 temp;
2865 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2866 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2867 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2868 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2869 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2870 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2871 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2872 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2875 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2876 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2877 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2878 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2881 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2882 temp &= ~SBI_SSCCTL_DISABLE;
2883 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2931 u32 reg, temp;
2955 temp = I915_READ(PCH_DPLL_SEL);
2956 temp |= TRANS_DPLL_ENABLE(pipe);
2959 temp |= sel;
2961 temp &= ~sel;
2962 I915_WRITE(PCH_DPLL_SEL, temp);
2977 temp = I915_READ(reg);
2978 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2981 temp |= (TRANS_DP_OUTPUT_ENABLE |
2983 temp |= bpc << 9; /* same format but at 11:9 */
2986 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2988 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2992 temp |= TRANS_DP_PORT_SEL_B;
2995 temp |= TRANS_DP_PORT_SEL_C;
2998 temp |= TRANS_DP_PORT_SEL_D;
3004 I915_WRITE(reg, temp);
3131 u32 temp;
3133 temp = I915_READ(dslreg);
3135 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3136 if (wait_for(I915_READ(dslreg) != temp, 5))
3192 u32 temp;
3207 temp = I915_READ(PCH_LVDS);
3208 if ((temp & LVDS_PORT_EN) == 0)
3209 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3395 u32 reg, temp;
3434 temp = I915_READ(reg);
3435 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3437 temp |= TRANS_DP_PORT_SEL_NONE;
3438 I915_WRITE(reg, temp);
3441 temp = I915_READ(PCH_DPLL_SEL);
3442 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3443 I915_WRITE(PCH_DPLL_SEL, temp);
4203 unsigned int temp = n;
4208 while (temp != 1) {
4210 temp = temp >> 1;
5557 uint32_t temp;
5559 temp = I915_READ(SOUTH_CHICKEN1);
5560 if (temp & FDI_BC_BIFURCATION_SELECT)
5566 temp |= FDI_BC_BIFURCATION_SELECT;
5568 I915_WRITE(SOUTH_CHICKEN1, temp);