895 	u32 val;
899 	val = I915_READ(reg);
900 	cur_state = !!(val & DPLL_VCO_ENABLE);
949 	u32 val;
957 		val = I915_READ(reg);
958 		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
961 	val = I915_READ(reg);
962 	cur_state = !!(val & FDI_TX_ENABLE);
975 	u32 val;
979 	val = I915_READ(reg);
980 	cur_state = !!(val & FDI_RX_ENABLE);
992 	u32 val;
1003 	val = I915_READ(reg);
1004 	if(!(val & FDI_TX_PLL_ENABLE))
1012 	u32 val;
1015 	val = I915_READ(reg);
1016 	if(!(val & FDI_RX_PLL_ENABLE))
1024 	u32 val;
1036 	val = I915_READ(pp_reg);
1037 	if (!(val & PANEL_POWER_ON) ||
1038 	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1053 	u32 val;
1067 		val = I915_READ(reg);
1068 		cur_state = !!(val & PIPECONF_ENABLE);
1080 	u32 val;
1084 	val = I915_READ(reg);
1085 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1099 	u32 val;
1105 		val = I915_READ(reg);
1106 		if(val & DISPLAY_PLANE_ENABLE)
1115 		val = I915_READ(reg);
1116 		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 		if((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1129 	u32 val;
1134 			val = I915_READ(reg);
1135 			if(val & SP_ENABLE)
1141 		val = I915_READ(reg);
1142 		if(val & SPRITE_ENABLE)
1147 		val = I915_READ(reg);
1148 		if(val & DVS_ENABLE)
1156 	u32 val;
1164 	val = I915_READ(PCH_DREF_CONTROL);
1165 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1175 	u32 val;
1179 	val = I915_READ(reg);
1180 	enabled = !!(val & TRANS_ENABLE);
1187 			    enum pipe pipe, u32 port_sel, u32 val)
1189 	if ((val & DP_PORT_EN) == 0)
1198 		if ((val & DP_PIPE_MASK) != (pipe << 30))
1205 			      enum pipe pipe, u32 val)
1207 	if ((val & SDVO_ENABLE) == 0)
1211 		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1214 		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1221 			      enum pipe pipe, u32 val)
1223 	if ((val & LVDS_PORT_EN) == 0)
1227 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1230 		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1237 			      enum pipe pipe, u32 val)
1239 	if ((val & ADPA_DAC_ENABLE) == 0)
1242 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1245 		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1254 	u32 val = I915_READ(reg);
1255 	if(dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1259 	if (HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 	     && (val & DP_PIPEB_SELECT))
1267 	u32 val = I915_READ(reg);
1268 	if(hdmi_pipe_enabled(dev_priv, pipe, val))
1272 	if (HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273 	     && (val & SDVO_PIPE_B_SELECT))
1281 	u32 val;
1288 	val = I915_READ(reg);
1289 	if(adpa_pipe_enabled(dev_priv, pipe, val))
1294 	val = I915_READ(reg);
1295 	if(lvds_pipe_enabled(dev_priv, pipe, val))
1320 	u32 val;
1332 	val = I915_READ(reg);
1333 	val |= DPLL_VCO_ENABLE;
1336 	I915_WRITE(reg, val);
1339 	I915_WRITE(reg, val);
1342 	I915_WRITE(reg, val);
1359 	u32 val;
1369 	val = I915_READ(reg);
1370 	val &= ~DPLL_VCO_ENABLE;
1371 	I915_WRITE(reg, val);
1471 	uint32_t reg, val, pipeconf_val;
1488 		val = I915_READ(reg);
1489 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1490 		I915_WRITE(reg, val);
1494 	val = I915_READ(reg);
1502 		val &= ~PIPECONF_BPC_MASK;
1503 		val |= pipeconf_val & PIPECONF_BPC_MASK;
1506 	val &= ~TRANS_INTERLACE_MASK;
1510 			val |= TRANS_LEGACY_INTERLACED_ILK;
1512 			val |= TRANS_INTERLACED;
1514 		val |= TRANS_PROGRESSIVE;
1516 	I915_WRITE(reg, val | TRANS_ENABLE);
1524 	u32 val, pipeconf_val;
1534 	val = I915_READ(_TRANSA_CHICKEN2);
1535 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1536 	I915_WRITE(_TRANSA_CHICKEN2, val);
1538 	val = TRANS_ENABLE;
1543 		val |= TRANS_INTERLACED;
1545 		val |= TRANS_PROGRESSIVE;
1547 	I915_WRITE(LPT_TRANSCONF, val);
1556 	uint32_t reg, val;
1566 	val = I915_READ(reg);
1567 	val &= ~TRANS_ENABLE;
1568 	I915_WRITE(reg, val);
1576 		val = I915_READ(reg);
1577 		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1578 		I915_WRITE(reg, val);
1584 	u32 val;
1586 	val = I915_READ(LPT_TRANSCONF);
1587 	val &= ~TRANS_ENABLE;
1588 	I915_WRITE(LPT_TRANSCONF, val);
1594 	val = I915_READ(_TRANSA_CHICKEN2);
1595 	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1596 	I915_WRITE(_TRANSA_CHICKEN2, val);
1620 	u32 val;
1648 	val = I915_READ(reg);
1649 	if (val & PIPECONF_ENABLE)
1652 	I915_WRITE(reg, val | PIPECONF_ENABLE);
1674 	u32 val;
1688 	val = I915_READ(reg);
1689 	if ((val & PIPECONF_ENABLE) == 0)
1692 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1721 	u32 val;
1727 	val = I915_READ(reg);
1728 	if (val & DISPLAY_PLANE_ENABLE)
1731 	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1748 	u32 val;
1751 	val = I915_READ(reg);
1752 	if ((val & DISPLAY_PLANE_ENABLE) == 0)
1755 	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
4469 		/* Use SSC source */
4477 		/* Use bend source */
5030 	u32 val, final;
5069 	val = I915_READ(PCH_DREF_CONTROL);
5071 	/* As we must carefully and slowly disable/enable each source in turn,
5075 	final = val;
5104 	if (final == val)
5107 	/* Always enable nonspread source */
5108 	val &= ~DREF_NONSPREAD_SOURCE_MASK;
5111 		val |= DREF_NONSPREAD_CK505_ENABLE;
5113 		val |= DREF_NONSPREAD_SOURCE_ENABLE;
5116 		val &= ~DREF_SSC_SOURCE_MASK;
5117 		val |= DREF_SSC_SOURCE_ENABLE;
5122 			val |= DREF_SSC1_ENABLE;
5124 			val &= ~DREF_SSC1_ENABLE;
5127 		I915_WRITE(PCH_DREF_CONTROL, val);
5131 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133 		/* Enable CPU source on CPU attached eDP */
5137 				val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5140 				val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5142 			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5144 		I915_WRITE(PCH_DREF_CONTROL, val);
5150 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5153 		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5155 		I915_WRITE(PCH_DREF_CONTROL, val);
5159 		/* Turn off the SSC source */
5160 		val &= ~DREF_SSC_SOURCE_MASK;
5161 		val |= DREF_SSC_SOURCE_DISABLE;
5164 		val &= ~DREF_SSC1_ENABLE;
5166 		I915_WRITE(PCH_DREF_CONTROL, val);
5171 	BUG_ON(val != final);
5378 	uint32_t val;
5380 	val = 0;
5384 		val |= PIPECONF_6BPC;
5387 		val |= PIPECONF_8BPC;
5390 		val |= PIPECONF_10BPC;
5393 		val |= PIPECONF_12BPC;
5401 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5404 		val |= PIPECONF_INTERLACED_ILK;
5406 		val |= PIPECONF_PROGRESSIVE;
5409 		val |= PIPECONF_COLOR_RANGE_SELECT;
5411 	I915_WRITE(PIPECONF(pipe), val);
5484 	uint32_t val;
5486 	val = 0;
5489 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5492 		val |= PIPECONF_INTERLACED_ILK;
5494 		val |= PIPECONF_PROGRESSIVE;
5496 	I915_WRITE(PIPECONF(cpu_transcoder), val);
7867 	/* Compute a starting value for pipe_config->pipe_bpp taking the source
7869 	 * source plane bpp so that dithering can be selected on mismatches
8861 	uint32_t val;
8863 	val = I915_READ(PCH_DPLL(pll->id));
8864 	hw_state->dpll = val;
8868 	return val & DPLL_VCO_ENABLE;
8874 	uint32_t reg, val;
8880 	val = I915_READ(reg);
8881 	val |= DPLL_VCO_ENABLE;
8882 	I915_WRITE(reg, val);
8892 	uint32_t reg, val;
8901 	val = I915_READ(reg);
8902 	val &= ~DPLL_VCO_ENABLE;
8903 	I915_WRITE(reg, val);
9714 	u32 reg, val;
9720 	val = I915_READ(reg);
9722 	if ((val & DISPLAY_PLANE_ENABLE) &&
9723 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10117 		u32 source;
10193 		error->pipe[i].source = I915_READ(PIPESRC(i));

Indexes created Tue Jul 24 14:28:13 CEST 2018